mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
045474be5e
Apple SoCs have an integrated NVMe controller that isn't connected over a PCIe bus. In preparation for adding support for this NVMe controller, split out the PCI support into its own file. This file is selected through a new CONFIG_NVME_PCI Kconfig option, so do a wholesale replacement of CONFIG_NVME with CONFIG_NVME_PCI. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
89 lines
2.3 KiB
Text
89 lines
2.3 KiB
Text
CONFIG_ARM=y
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CONFIG_GIC_V3_ITS=y
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CONFIG_TARGET_LS2080AQDS=y
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CONFIG_SYS_TEXT_BASE=0x80400000
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CONFIG_SYS_MALLOC_LEN=0x0220000
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=3
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CONFIG_ENV_SIZE=0x20000
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CONFIG_ENV_OFFSET=0x300000
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CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
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CONFIG_SPL_TEXT_BASE=0x1800a000
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CONFIG_FSL_USE_PCA9547_MUX=y
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CONFIG_FSL_LS_PPA=y
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CONFIG_SPL_MMC=y
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL=y
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CONFIG_AHCI=y
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CONFIG_REMAKE_ELF=y
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CONFIG_MP=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_DYNAMIC_SYS_CLK_FREQ=y
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CONFIG_SD_BOOT=y
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CONFIG_BOOTDELAY=10
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
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CONFIG_BOOTCOMMAND="mmc read 0x80200000 0x6800 0x800; fsl_mc apply dpl 0x80200000 && mmc read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
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CONFIG_SPL_ENV_SUPPORT=y
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CONFIG_SPL_I2C=y
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CONFIG_SPL_MPC8XXX_INIT_DDR=y
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CONFIG_CMD_GREPENV=y
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CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_NAND=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_DATE=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_EMBED=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_SATA=y
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CONFIG_SATA_CEVA=y
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CONFIG_DYNAMIC_DDR_CLK_FREQ=y
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CONFIG_DDR_ECC=y
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CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_EARLY_INIT=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB_10G=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_NVME_PCI=y
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CONFIG_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_LAYERSCAPE_RC=y
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CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
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CONFIG_DM_SCSI=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_FSL_QSPI=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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