mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
c42ffff02a
The mem_manuf is not in the correct order according to the string table. This causes cros_bundle_firmware to get the BL2 settings in the wrong order. This patch fixes the same. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
98 lines
3.3 KiB
C
98 lines
3.3 KiB
C
/*
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* Copyright (c) 2012 The Chromium OS Authors.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_EXYNOS_SPL_H__
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#define __ASM_ARCH_EXYNOS_SPL_H__
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#include <asm/arch-exynos/dmc.h>
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enum boot_mode {
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/*
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* Assign the OM pin values for respective boot modes.
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* Exynos4 does not support spi boot and the mmc boot OM
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* pin values are the same across Exynos4 and Exynos5.
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*/
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BOOT_MODE_MMC = 4,
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BOOT_MODE_SERIAL = 20,
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/* Boot based on Operating Mode pin settings */
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BOOT_MODE_OM = 32,
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BOOT_MODE_USB, /* Boot using USB download */
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};
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#ifndef __ASSEMBLY__
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/* Parameters of early board initialization in SPL */
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struct spl_machine_param {
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/* Add fields as and when required */
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u32 signature;
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u32 version; /* Version number */
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u32 size; /* Size of block */
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/**
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* Parameters we expect, in order, terminated with \0. Each parameter
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* is a single character representing one 32-bit word in this
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* structure.
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*
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* Valid characters in this string are:
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*
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* Code Name
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* v mem_iv_size
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* m mem_type
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* u uboot_size
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* b boot_source
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* f frequency_mhz (memory frequency in MHz)
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* a ARM clock frequency in MHz
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* s serial base address
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* i i2c base address for early access (meant for PMIC)
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* r board rev GPIO numbers used to read board revision
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* (lower halfword=bit 0, upper=bit 1)
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* M Memory Manufacturer name
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* \0 termination
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*/
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char params[12]; /* Length must be word-aligned */
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u32 mem_iv_size; /* Memory channel interleaving size */
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enum ddr_mode mem_type; /* Type of on-board memory */
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/*
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* U-boot size - The iROM mmc copy function used by the SPL takes a
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* block count paramter to describe the u-boot size unlike the spi
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* boot copy function which just uses the u-boot size directly. Align
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* the u-boot size to block size (512 bytes) when populating the SPL
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* table only for mmc boot.
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*/
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u32 uboot_size;
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enum boot_mode boot_source; /* Boot device */
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unsigned frequency_mhz; /* Frequency of memory in MHz */
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unsigned arm_freq_mhz; /* ARM Frequency in MHz */
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u32 serial_base; /* Serial base address */
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u32 i2c_base; /* i2c base address */
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u32 board_rev_gpios; /* Board revision GPIOs */
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enum mem_manuf mem_manuf; /* Memory Manufacturer */
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} __attribute__((__packed__));
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#endif
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/**
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* Validate signature and return a pointer to the parameter table. If the
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* signature is invalid, call panic() and never return.
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*
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* @return pointer to the parameter table if signature matched or never return.
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*/
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struct spl_machine_param *spl_get_machine_params(void);
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#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */
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