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Michal Simek 64fc7fc887 soc: xilinx: versal-net: Add soc_xilinx_versal_net driver 
Add soc_xilinx_versal_net driver to identify the family & revision of
versal-net SoC. Add Kconfig option CONFIG_SOC_XILINX_VERSAL_NET to
enable/disable this driver. To enable this driver by default, add this
config to xilinx_versal_net_virt_defconfig file. This driver will be
probed using platdata U_BOOT_DEVICE structure which is specified in
mach-versal-net/cpu.c.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/613d6bcffd9070f62cf348079ed16c120f8fc56f.1668612993.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
..
ti soc: ti: pruss: Add a platform driver for PRUSS in TI SoCs 2021-07-15 17:56:04 +05:30
Kconfig soc: xilinx: versal-net: Add soc_xilinx_versal_net driver 2022-11-22 15:02:07 +01:00
Makefile soc: xilinx: versal-net: Add soc_xilinx_versal_net driver 2022-11-22 15:02:07 +01:00
soc-uclass.c dm: define LOG_CATEGORY for all uclass 2021-07-06 10:38:03 -06:00
soc_sandbox.c test: Add tests for SOC uclass 2020-07-25 14:46:57 -06:00
soc_ti_k3.c soc: soc_ti_k3: identify j7200 SR2.0 SoCs 2022-07-06 14:30:51 -04:00
soc_xilinx_versal.c soc: xilinx: versal: fix out of bounds array access 2022-05-13 09:10:02 +02:00
soc_xilinx_versal_net.c soc: xilinx: versal-net: Add soc_xilinx_versal_net driver 2022-11-22 15:02:07 +01:00
soc_xilinx_zynqmp.c soc: xilinx: zynqmp: Mark soc_xilinx_zynqmp_get_machine() as static 2022-10-10 12:28:08 +02:00