mirror of
https://github.com/AsahiLinux/u-boot
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b2412dd5de
This board is useful for benchmarking overall U-Boot performance. Enable the bootstage feature so we get a report. Since this returns to the boot rom before finishing executing board_init_r() in SPL, add a few bootstage calls so that we can collect timing from TPL. For the stash region, use a portion of SRAM, 64KB below the stack top. This allows the TPL image to be up to nearly 120KB (it is typically about 64KB). SPL normally runs from SDRAM at 0, so can use the same stash region. Signed-off-by: Simon Glass <sjg@chromium.org>
114 lines
2.5 KiB
C
114 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <bootstage.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <spl.h>
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#include <version.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <linux/bitops.h>
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#include <linux/kconfig.h>
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#if CONFIG_IS_ENABLED(BANNER_PRINT)
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#include <timestamp.h>
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#endif
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#define TIMER_LOAD_COUNT_L 0x00
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#define TIMER_LOAD_COUNT_H 0x04
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_EN 0x1
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#define TIMER_FMODE BIT(0)
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#define TIMER_RMODE BIT(1)
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__weak void rockchip_stimer_init(void)
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{
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#if defined(CONFIG_ROCKCHIP_STIMER_BASE)
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/* If Timer already enabled, don't re-init it */
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u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
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if (reg & TIMER_EN)
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return;
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#ifndef CONFIG_ARM64
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asm volatile("mcr p15, 0, %0, c14, c0, 0"
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: : "r"(CONFIG_COUNTER_FREQUENCY));
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#endif
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writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
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writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
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TIMER_CONTROL_REG);
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#endif
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
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/*
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* Debug UART can be used from here if required:
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*
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* debug_uart_init();
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* printch('a');
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* printhex8(0x1234);
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* printascii("string");
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*/
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debug_uart_init();
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#ifdef CONFIG_TPL_BANNER_PRINT
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printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
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U_BOOT_TIME ")\n");
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#endif
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#endif
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/* Init secure timer */
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rockchip_stimer_init();
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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/* Init ARM arch timer */
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if (IS_ENABLED(CONFIG_SYS_ARCH_TIMER))
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timer_init();
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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printf("DRAM init failed: %d\n", ret);
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return;
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}
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}
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int board_return_to_bootrom(struct spl_image_info *spl_image,
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struct spl_boot_device *bootdev)
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{
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#ifdef CONFIG_BOOTSTAGE_STASH
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int ret;
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bootstage_mark_name(BOOTSTAGE_ID_END_TPL, "end tpl");
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ret = bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
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CONFIG_BOOTSTAGE_STASH_SIZE);
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if (ret)
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debug("Failed to stash bootstage: err=%d\n", ret);
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#endif
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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return 0;
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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