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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
63 lines
2.2 KiB
C
63 lines
2.2 KiB
C
/*
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* Cross Bar Switch Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CROSSBAR_H__
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#define __CROSSBAR_H__
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/*********************************************************************
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* Cross-bar switch (XBS)
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*********************************************************************/
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typedef struct xbs {
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u32 prs1; /* 0x100 Priority Register Slave 1 */
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u32 res1[3]; /* 0x104 - 0F */
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u32 crs1; /* 0x110 Control Register Slave 1 */
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u32 res2[187]; /* 0x114 - 0x3FF */
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u32 prs4; /* 0x400 Priority Register Slave 4 */
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u32 res3[3]; /* 0x404 - 0F */
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u32 crs4; /* 0x410 Control Register Slave 4 */
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u32 res4[123]; /* 0x414 - 0x5FF */
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u32 prs6; /* 0x600 Priority Register Slave 6 */
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u32 res5[3]; /* 0x604 - 0F */
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u32 crs6; /* 0x610 Control Register Slave 6 */
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u32 res6[59]; /* 0x614 - 0x6FF */
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u32 prs7; /* 0x700 Priority Register Slave 7 */
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u32 res7[3]; /* 0x704 - 0F */
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u32 crs7; /* 0x710 Control Register Slave 7 */
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} xbs_t;
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/* Bit definitions and macros for PRS group */
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#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */
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#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */
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#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */
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#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */
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#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */
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#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */
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#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */
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/* Bit definitions and macros for CRS group */
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#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */
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#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */
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#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */
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#define XBS_CRS_RO (0x80000000) /* Read Only */
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#define XBS_CRS_PCTL_PARK_FIELD (0)
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#define XBS_CRS_PCTL_PARK_ON_LAST (1)
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#define XBS_CRS_PCTL_PARK_NONE (2)
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#define XBS_CRS_PCTL_PARK_CORE (0)
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#define XBS_CRS_PCTL_PARK_EDMA (1)
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#define XBS_CRS_PCTL_PARK_FEC0 (2)
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#define XBS_CRS_PCTL_PARK_FEC1 (3)
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#define XBS_CRS_PCTL_PARK_PCI (5)
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#define XBS_CRS_PCTL_PARK_USB (6)
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#define XBS_CRS_PCTL_PARK_SBF (7)
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#endif /* __CROSSBAR_H__ */
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