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https://github.com/AsahiLinux/u-boot
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ee7bb5be35
This patch enable work for ar933x SOC. Signed-off-by: Wills Wang <wills.wang@live.com>
280 lines
6.6 KiB
ArmAsm
280 lines
6.6 KiB
ArmAsm
/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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* Based on Atheros LSDK/QSDK and u-boot_mod project
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <mach/ar71xx_regs.h>
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#define SET_BIT(val, bit) ((val) | (1 << (bit)))
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#define SET_PLL_PD(val) SET_BIT(val, 30)
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#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16)
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#define PLL_BYPASS(val) SET_BIT(val, 2)
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#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
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(((0x3F & divint) << 10) | \
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((0x1F & refdiv) << 16) | \
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((0x1 & range) << 21) | \
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((0x7 & outdiv) << 23) )
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#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
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(((0x3 & (cpudiv - 1)) << 5) | \
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((0x3 & (ddrdiv - 1)) << 10) | \
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((0x3 & (ahbdiv - 1)) << 15) )
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/*
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* PLL_CPU_CONFIG_VAL
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*
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* Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
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* After PLL configuration we need to clear this bit
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*
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* Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
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*
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* bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL)
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* => 32 (0x20) VCOOUT = XTAL * DIV_INT
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* bits 16..20 (5bit) REFDIV (Reference clock divider)
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* => 1 (0x1) [Must start at values 1]
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* bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL)
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* => 0 (0x0) [Doesn't impact clock values]
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* bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output)
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* => 1 (0x1) [0 is illegal!]
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* PLLOUT = VCOOUT * (1/2^OUTDIV)
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*/
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/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
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#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1)
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/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
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#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1)
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/*
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* PLL_CLK_CONTROL_VAL
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*
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* In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
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* After PLL configuration we need to clear this bit
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*
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* Values written into CPU Clock Control Register CLOCK_CONTROL
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*
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* bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test.
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* Software must enable the CPU PLL for normal and
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* then set this bit to 0)
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* bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1)
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* CPU_CLK = PLLOUT / CPU_POST_DIV
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* bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1)
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* DDR_CLK = PLLOUT / DDR_POST_DIV
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* bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2)
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* AHB_CLK = PLLOUT / AHB_POST_DIV
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*
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*/
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#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
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.text
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.set noreorder
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LEAF(lowlevel_init)
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/* These three WLAN_RESET will avoid original issue */
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li t3, 0x03
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1:
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li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
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lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
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ori t1, t1, 0x0800
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sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
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nop
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lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
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li t2, 0xfffff7ff
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and t1, t1, t2
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sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
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nop
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addi t3, t3, -1
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bnez t3, 1b
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nop
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li t2, 0x20
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2:
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beqz t2, 1b
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nop
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addi t2, t2, -1
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lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
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andi t1, t5, 0x10
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bnez t1, 2b
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nop
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li t1, 0x02110E
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sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
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nop
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/* RTC Force Wake */
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li t0, CKSEG1ADDR(AR933X_RTC_BASE)
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li t1, 0x03
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sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
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nop
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nop
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/* RTC Reset */
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li t1, 0x00
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sw t1, AR933X_RTC_REG_RESET(t0)
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nop
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nop
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li t1, 0x01
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sw t1, AR933X_RTC_REG_RESET(t0)
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nop
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nop
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/* Wait for RTC in on state */
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1:
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lw t1, AR933X_RTC_REG_STATUS(t0)
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andi t1, t1, 0x02
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beqz t1, 1b
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nop
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/* Program ki/kd */
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li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
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andi t1, t5, 0x01 # t5 BOOT_STRAP
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bnez t1, 1f
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nop
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li t1, 0x19e82f01
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b 2f
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nop
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1:
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li t1, 0x18e82f01
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2:
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sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
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/* Program phase shift */
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lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
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li t2, 0xc07fffff
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and t1, t1, t2
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li t2, 0x800000
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or t1, t1, t2
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sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
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nop
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/* in some cases, the SoC doesn't start with higher clock on AHB */
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li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
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li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
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sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
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nop
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/* Set SETTLE_TIME in CPU PLL */
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andi t1, t5, 0x01 # t5 BOOT_STRAP
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bnez t1, 1f
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nop
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li t1, 0x0352
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b 2f
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nop
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1:
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li t1, 0x0550
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2:
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sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
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nop
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/* Set nint, frac, refdiv, outdiv, range according to xtal */
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0:
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andi t1, t5, 0x01 # t5 BOOT_STRAP
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bnez t1, 1f
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nop
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li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
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b 2f
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nop
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1:
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li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
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2:
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sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
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nop
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1:
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lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
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li t2, 0x80000000
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and t1, t1, t2
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bnez t1, 1b
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nop
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/* Put frac bit19:10 configuration */
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li t1, 0x1003E8
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sw t1, AR933X_PLL_DITHER_FRAC_REG(t0)
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nop
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/* Clear PLL power down bit in CPU PLL configuration */
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andi t1, t5, 0x01 # t5 BOOT_STRAP
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bnez t1, 1f
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nop
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li t1, PLL_CPU_CONFIG_VAL_25M
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b 2f
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nop
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1:
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li t1, PLL_CPU_CONFIG_VAL_40M
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2:
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sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
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nop
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/* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
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1:
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lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
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li t2, 0x80000000
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and t1, t1, t2
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bnez t1, 1b
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nop
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/* Confirm DDR PLL lock */
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li t3, 100
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li t4, 0
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2:
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addi t4, t4, 1
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bgt t4, t3, 0b
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nop
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li t3, 5
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3:
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/* Clear do_meas */
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li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
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lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
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li t2, 0xBFFFFFFF
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and t1, t1, t2
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sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
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nop
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li t2, 10
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1:
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subu t2, t2, 1
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bnez t2, 1b
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nop
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/* Set do_meas */
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li t2, 0x40000000
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or t1, t1, t2
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sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
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nop
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/* Check meas_done */
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1:
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lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
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andi t1, t1, 0x8
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beqz t1, 1b
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nop
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lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
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li t2, 0x007FFFF8
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and t1, t1, t2
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srl t1, t1, 3
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li t2, 0x4000
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bgt t1, t2, 2b
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nop
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addi t3, t3, -1
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bnez t3, 3b
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nop
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/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
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li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
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li t1, PLL_CLK_CONTROL_VAL
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sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
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nop
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nop
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jr ra
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nop
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END(lowlevel_init)
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