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Add support for lx2160a SoC -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEorkTmaQ1QAtDiYw67UVZlNoLnbQFAlwOzFoACgkQ7UVZlNoL nbQUdQ//SRRBfjUe8RYTbojvTGQav0GTxnMkz4GFSrqu0nvGMW2YSlheOMqq72sg rK5mQqDvdkItCn+G8AZ5NV2ijkQ7NQWCfqL3EtApzTpv6qjfgv7xvopz8q4NZvzB Wp+4cFf9YQjNwhJ7kLvWHB7SBiz9AfMYRAj9cscH9xsGL3HxPj62WDfwyK/QXana KIxRKQ26/1AdOZy272yv70vlFj4IwForxV3ACimsWRuYcb8yre3pE0tD7XpMCSNv 9GOfL7r4LS7U0+QnJoVeYLMhttRvOGJNUYtO2+ImO5NC3u9v8ehYEQ3FjGmM69CB vuPDQBDQc+Ap+Iu3k18PYSstp+mc9fbe9SQdlx6ARAecQqWTN4EOhf8s3m2bQq3S B58I0Zvowcdm8V2JKdXw94UqZX862U8PWH0BmcuX+4k+kRDwwU4XQY2nLp+Htz1w 2q6vEdKGj7YUOaomx9fmKRL+9BFGoD+M9mTiHOwzqwxy6Pa9VkruSvMErM7p2l/z xI/Q+xPJhyk5TXgZRsz4Nat59WpifWruibKEd4PArQ446heHWmzLWjw/MWiFyd/H agCdpDZVJ8R7h1Krs+Ez8XjR1Qcg0gs+CdNBuvqxzOpMQGGonXA1nwi8YfHykhII urfoC8pew1yxiLGw7J2JSX808HV/09WCSEsrOOhE3T78rXTDlS4= =aT7d -----END PGP SIGNATURE----- Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq Add TFA boot flow for some Layerscape platforms Add support for lx2160a SoC [trini: Add a bunch of missing MAINTAINERS entries] Signed-off-by: Tom Rini <trini@konsulko.com> |
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.. | ||
cpld.c | ||
cpld.h | ||
ddr.c | ||
ddr.h | ||
eth.c | ||
Kconfig | ||
ls1046ardb.c | ||
ls1046ardb_pbi.cfg | ||
ls1046ardb_qspi_pbi.cfg | ||
ls1046ardb_rcw_emmc.cfg | ||
ls1046ardb_rcw_qspi.cfg | ||
ls1046ardb_rcw_sd.cfg | ||
MAINTAINERS | ||
Makefile | ||
README |
Overview -------- The LS1046A Reference Design Board (RDB) is a high-performance computing, evaluation, and development platform that supports the QorIQ LS1046A LayerScape Architecture processor. The LS1046ARDB provides SW development platform for the Freescale LS1046A processor series, with a complete debugging environment. The LS1046A RDB is lead-free and RoHS-compliant. LS1046A SoC Overview -------------------- Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A SoC overview. LS1046ARDB board Overview ----------------------- - SERDES1 Connections, 4 lanes supporting: - Lane0: XFI with x1 RJ45 connector - Lane1: XFI Cage - Lane2: SGMII.5 - Lane3: SGMII.6 - SERDES2 Connections, 4 lanes supporting: - Lane0: PCIe1 with miniPCIe slot - Lane1: PCIe2 with PCIe x2 slot - Lane2: PCIe3 with PCIe x4 slot - Lane3: SATA - DDR Controller - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s -IFC/Local Bus - One 512 MB NAND flash with ECC support - CPLD connection - USB 3.0 - one Type A port, one Micro-AB port - SDHC: connects directly to a full SD/MMC slot - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz) - 4 I2C controllers - UART - Two 4-pin serial ports at up to 115.2 Kbit/s - Two DB9 D-Type connectors supporting one Serial port each - ARM JTAG support Memory map from core's view ---------------------------- Start Address End Address Description Size 0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB 0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB 0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB 0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB 0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB 0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB 0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB 0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M 0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M 0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB 0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G 0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G 0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G QSPI flash map: Start Address End Address Description Size 0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB 0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB 0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB 0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB 0x00_4060_0000 - 0x00_408F_FFFF Secure boot header + bootscript 3MB 0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB 0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB 0x00_4098_0000 - 0x00_40FF_FFFF Reserved 6MB 0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB Booting Options --------------- a) QSPI boot b) SD boot c) eMMC boot