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8ed9604613
add support for the TI OMAP2420 processor and its H4 reference board * Patch by Christian Pellegrin, 24 Sep 2004: Added support for NE2000 compatible (DP8390, DP83902) NICs.
237 lines
6.9 KiB
ArmAsm
237 lines
6.9 KiB
ArmAsm
/*
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* Board specific setup info
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*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/omap2420.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/clocks.h>
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_TEXT_BASE:
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.word TEXT_BASE /* sdram load addr from config.mk */
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#ifdef CONFIG_PARTIAL_SRAM
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/**************************************************************************
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* cpy_clk_code: relocates clock code into SRAM where its safer to execute
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* R1 = SRAM destination address.
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*************************************************************************/
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.global cpy_clk_code
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cpy_clk_code:
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/* Copy DPLL code into SRAM */
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adr r0, go_to_speed /* get addr of clock setting code */
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mov r2, #384 /* r2 size to copy (div by 32 bytes) */
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mov r1, r1 /* r1 <- dest address (passed in) */
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add r2, r2, r0 /* r2 <- source end address */
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next2:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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bne next2
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mov pc, lr /* back to caller */
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/* ****************************************************************************
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* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
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* -executed from SRAM.
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* R0 = PRCM_CLKCFG_CTRL - addr of valid reg
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* R1 = CM_CLKEN_PLL - addr dpll ctlr reg
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* R2 = dpll value
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* R3 = CM_IDLEST_CKGEN - addr dpll lock wait
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******************************************************************************/
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.global go_to_speed
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go_to_speed:
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sub sp, sp, #0x4 /* get some stack space */
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str r4, [sp] /* save r4's value */
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/* move into fast relock bypass */
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ldr r8, pll_ctl_add
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mov r4, #0x2
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str r4, [r8]
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ldr r4, pll_stat
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block:
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ldr r8, [r4] /* wait for bypass to take effect */
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and r8, r8, #0x3
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cmp r8, #0x1
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bne block
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/* set new dpll dividers _after_ in bypass */
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ldr r4, pll_div_add
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ldr r8, pll_div_val
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str r8, [r4]
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/* now prepare GPMC (flash) for new dpll speed */
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/* flash needs to be stable when we jump back to it */
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ldr r4, cfg3_0_addr
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ldr r8, cfg3_0_val
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str r8, [r4]
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ldr r4, cfg4_0_addr
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ldr r8, cfg4_0_val
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str r8, [r4]
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ldr r4, cfg1_0_addr
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ldr r8, [r4]
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orr r8, r8, #0x3 /* up gpmc divider */
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str r8, [r4]
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/* setup to 2x loop though code. The first loop pre-loads the
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* icache, the 2nd commits the prcm config, and locks the dpll
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*/
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mov r4, #0x1000 /* spin spin spin */
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mov r8, #0x4 /* first pass condition & set registers */
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cmp r8, #0x4
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2:
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ldrne r8, [r3] /* DPLL lock check */
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and r8, r8, #0x7
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cmp r8, #0x2
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beq 4f
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3:
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subeq r8, r8, #0x1
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streq r8, [r0] /* commit dividers (2nd time) */
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nop
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lloop1:
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sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
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nop
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cmp r4, #0x0
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bne lloop1
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mov r4, #0x40000
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cmp r8, #0x1
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nop
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streq r2, [r1] /* lock dpll (2nd time) */
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nop
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lloop2:
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sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
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nop
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cmp r4, #0x0
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bne lloop2
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mov r4, #0x40000
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cmp r8, #0x1
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nop
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ldreq r8, [r3] /* get lock condition for dpll */
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cmp r8, #0x4 /* first time though? */
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bne 2b
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moveq r8, #0x2 /* set to dpll check condition. */
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beq 3b /* if condition not true branch */
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4:
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ldr r4, [sp]
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add sp, sp, #0x4 /* return stack space */
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mov pc, lr /* back to caller, locked */
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_go_to_speed: .word go_to_speed
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/* these constants need to be close for PIC code */
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cfg3_0_addr:
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.word GPMC_CONFIG3_0
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cfg3_0_val:
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.word H4_24XX_GPMC_CONFIG3_0
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cfg4_0_addr:
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.word GPMC_CONFIG4_0
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cfg4_0_val:
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.word H4_24XX_GPMC_CONFIG4_0
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cfg1_0_addr:
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.word GPMC_CONFIG1_0
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pll_ctl_add:
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.word CM_CLKEN_PLL
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pll_stat:
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.word CM_IDLEST_CKGEN
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pll_div_add:
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.word CM_CLKSEL1_PLL
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pll_div_val:
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.word DPLL_VAL /* DPLL setting (300MHz default) */
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#endif
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.globl platformsetup
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platformsetup:
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mov r3, r0 /* save skip information */
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#ifdef CONFIG_APTIX
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ldr r0, REG_SDRC_MCFG_0
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ldr r1, VAL_SDRC_MCFG_0
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str r1, [r0]
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ldr r0, REG_SDRC_MR_0
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ldr r1, VAL_SDRC_MR_0
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str r1, [r0]
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/* a ddr needs emr1 set here */
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ldr r0, REG_SDRC_SHARING
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ldr r1, VAL_SDRC_SHARING
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str r1, [r0]
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ldr r0, REG_SDRC_RFR_CTRL_0
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ldr r1, VAL_SDRC_RFR_CTRL_0
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str r1, [r0]
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/* little delay after init */
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mov r2, #0x1800
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1:
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subs r2, r2, #0x1
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bne 1b
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#endif
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#ifdef CONFIG_PARTIAL_SRAM
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ldr sp, SRAM_STACK
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str ip, [sp] /* stash old link register */
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mov ip, lr /* save link reg across call */
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mov r0, r3 /* pass skip info to s_init */
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bl s_init /* go setup pll,mux,memory */
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ldr ip, [sp] /* restore save ip */
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mov lr, ip /* restore link reg */
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#endif
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/* map interrupt controller */
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ldr r0, VAL_INTH_SETUP
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mcr p15, 0, r0, c15, c2, 4
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/* back to arch calling code */
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mov pc, lr
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/* the literal pools origin */
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.ltorg
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REG_CONTROL_STATUS:
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.word CONTROL_STATUS
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VAL_INTH_SETUP:
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.word PERIFERAL_PORT_BASE
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SRAM_STACK:
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.word LOW_LEVEL_SRAM_STACK
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#ifdef CONFIG_APTIX
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REG_SDRC_SHARING:
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.word SDRC_SHARING
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REG_SDRC_MCFG_0:
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.word SDRC_MCFG_0
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REG_SDRC_MR_0:
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.word SDRC_MR_0
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REG_SDRC_RFR_CTRL_0:
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.word SDRC_RFR_CTRL
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VAL_SDRC_SHARING:
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.word VAL_H4_SDRC_SHARING
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VAL_SDRC_MCFG_0:
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.word VAL_H4_SDRC_MCFG_0
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VAL_SDRC_MR_0:
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.word VAL_H4_SDRC_MR_0
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VAL_SDRC_RFR_CTRL_0:
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.word VAL_H4_SDRC_RFR_CTRL_0
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#endif
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