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22d238f25d
Entry for physical address 0x500000000 in memory map table for MMU configuration is spilling over and inadvertently making DDR available at higher address (above 4GB address space) get mapped as device memory (nGnRnE). Fix this by adjusting entry size. Tested on AM62A SK. Before this patch: => time crc32 0x881000000 0x20000000 crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca time: 1 minutes, 14.716 seconds After patch: => time crc32 0x881000000 0x20000000 crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca time: 2.710 seconds Acked-by: Andrew Davis <afd@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* K3: ARM64 MMU setup
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*
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* Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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* Suman Anna <s-anna@ti.com>
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* (This file is derived from arch/arm/mach-zynqmp/cpu.c)
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*
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*/
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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struct mm_region k3_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x1e780000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xa0000000UL,
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.phys = 0xa0000000UL,
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.size = 0x60000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x880000000UL,
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.phys = 0x880000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x500000000UL,
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.phys = 0x500000000UL,
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.size = 0x380000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = k3_mem_map;
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