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https://github.com/AsahiLinux/u-boot
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6645934646
spl_mmc_emmc_boot_partition return a number different from 0 if the partition is a boot one. We can have the uboot img for instance in a raw offset in emmc partition 0 so we would like to continue to load the next stage. If the user want to use EMMC as boot device allow him to use any part of the emmc and not only boot partition Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
334 lines
8.9 KiB
C
334 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* AM625: SoC specific initialization
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*
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* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
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* Suman Anna <s-anna@ti.com>
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*/
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include "sysfw-loader.h"
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#include "common.h"
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <dm/pinctrl.h>
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#define RTC_BASE_ADDRESS 0x2b1f0000
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#define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18)
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#define REG_K3RTC_KICK0 (RTC_BASE_ADDRESS + 0x70)
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#define REG_K3RTC_KICK1 (RTC_BASE_ADDRESS + 0x74)
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/* Magic values for lock/unlock */
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#define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13
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#define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0
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/*
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* This uninitialized global variable would normal end up in the .bss section,
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* but the .bss is cleared between writing and reading this variable, so move
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* it to the .data section.
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*/
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u32 bootindex __section(".data");
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static struct rom_extended_boot_data bootdata __section(".data");
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static void store_boot_info_from_rom(void)
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{
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bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
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memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
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sizeof(struct rom_extended_boot_data));
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}
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static void ctrl_mmr_unlock(void)
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{
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/* Unlock all WKUP_CTRL_MMR0 module registers */
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
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/* Unlock all CTRL_MMR0 module registers */
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mmr_unlock(CTRL_MMR0_BASE, 0);
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mmr_unlock(CTRL_MMR0_BASE, 1);
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mmr_unlock(CTRL_MMR0_BASE, 2);
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mmr_unlock(CTRL_MMR0_BASE, 4);
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mmr_unlock(CTRL_MMR0_BASE, 6);
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/* Unlock all MCU_CTRL_MMR0 module registers */
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mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
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/* Unlock PADCFG_CTRL_MMR padconf registers */
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mmr_unlock(PADCFG_MMR0_BASE, 1);
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mmr_unlock(PADCFG_MMR1_BASE, 1);
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}
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static __maybe_unused void enable_mcu_esm_reset(void)
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{
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/* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */
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u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
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stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK;
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writel(stat, CTRLMMR_MCU_RST_CTRL);
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}
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/*
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* RTC Erratum i2327 Workaround for Silicon Revision 1
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*
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* Due to a bug in initial synchronization out of cold power on,
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* IRQ status can get locked infinitely if we do not unlock RTC
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*
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* This workaround *must* be applied within 1 second of power on,
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* So, this is closest point to be able to guarantee the max
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* timing.
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*
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* https://www.ti.com/lit/er/sprz487c/sprz487c.pdf
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*/
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static __maybe_unused void rtc_erratumi2327_init(void)
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{
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u32 counter;
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/*
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* If counter has gone past 1, nothing we can do, leave
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* system locked! This is the only way we know if RTC
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* can be used for all practical purposes.
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*/
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counter = readl(REG_K3RTC_S_CNT_LSW);
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if (counter > 1)
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return;
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/*
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* Need to set this up at the very start
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* MUST BE DONE under 1 second of boot.
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*/
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writel(K3RTC_KICK0_UNLOCK_VALUE, REG_K3RTC_KICK0);
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writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1);
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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if (IS_ENABLED(CONFIG_CPU_V7R)) {
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setup_k3_mpu_regions();
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rtc_erratumi2327_init();
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}
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/*
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* Cannot delay this further as there is a chance that
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* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
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*/
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store_boot_info_from_rom();
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ctrl_mmr_unlock();
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/* Init DM early */
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spl_early_init();
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/*
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* Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and
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* MAIN_UART1 modules and continue regardless of the result of pinctrl.
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* Do this without probing the device, but instead by searching the
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* device that would request the given sequence number if probed. The
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* UARTs will be used by the DM firmware and TIFS firmware images
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* respectively and the firmware depend on SPL to initialize the pin
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* settings.
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*/
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ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
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if (!ret)
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pinctrl_select_state(dev, "default");
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ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
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if (!ret)
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pinctrl_select_state(dev, "default");
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preloader_console_init();
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/*
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* Allow establishing an early console as required for example when
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* doing a UART-based boot. Note that this console may not "survive"
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* through a SYSFW PM-init step and will need a re-init in some way
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* due to changing module clock frequencies.
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*/
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if (IS_ENABLED(CONFIG_K3_EARLY_CONS))
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early_console_init();
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/*
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* Configure and start up system controller firmware. Provide
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* the U-Boot console init function to the SYSFW post-PM configuration
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* callback hook, effectively switching on (or over) the console
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* output.
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*/
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if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
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ret = is_rom_loaded_sysfw(&bootdata);
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if (!ret)
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panic("ROM has not loaded TIFS firmware\n");
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k3_sysfw_loader(true, NULL, NULL);
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}
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/*
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* Force probe of clk_k3 driver here to ensure basic default clock
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* configuration is always done.
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*/
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if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(ti_clk),
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&dev);
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if (ret)
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printf("Failed to initialize clk-k3!\n");
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}
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/* Output System Firmware version info */
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k3_sysfw_print_ver();
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if (IS_ENABLED(CONFIG_ESM_K3)) {
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/* Probe/configure ESM0 */
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ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
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if (ret)
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printf("esm main init failed: %d\n", ret);
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/* Probe/configure MCUESM */
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ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev);
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if (ret)
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printf("esm mcu init failed: %d\n", ret);
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enable_mcu_esm_reset();
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}
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if (IS_ENABLED(CONFIG_K3_AM64_DDRSS)) {
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret)
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panic("DRAM init failed: %d\n", ret);
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}
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spl_enable_cache();
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}
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u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
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{
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u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
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u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
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MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
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u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
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MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
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switch (bootmode) {
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case BOOT_DEVICE_EMMC:
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if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
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return MMCSD_MODE_EMMCBOOT;
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if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
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return MMCSD_MODE_FS;
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return MMCSD_MODE_EMMCBOOT;
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case BOOT_DEVICE_MMC:
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if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK)
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return MMCSD_MODE_RAW;
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default:
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return MMCSD_MODE_FS;
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}
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}
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static u32 __get_backup_bootmedia(u32 devstat)
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{
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u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
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MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
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u32 bkup_bootmode_cfg =
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(devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
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MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
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switch (bkup_bootmode) {
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case BACKUP_BOOT_DEVICE_UART:
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return BOOT_DEVICE_UART;
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case BACKUP_BOOT_DEVICE_USB:
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return BOOT_DEVICE_USB;
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case BACKUP_BOOT_DEVICE_ETHERNET:
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return BOOT_DEVICE_ETHERNET;
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case BACKUP_BOOT_DEVICE_MMC:
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if (bkup_bootmode_cfg)
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return BOOT_DEVICE_MMC2;
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return BOOT_DEVICE_MMC1;
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case BACKUP_BOOT_DEVICE_SPI:
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return BOOT_DEVICE_SPI;
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case BACKUP_BOOT_DEVICE_I2C:
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return BOOT_DEVICE_I2C;
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case BACKUP_BOOT_DEVICE_DFU:
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if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
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return BOOT_DEVICE_USB;
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return BOOT_DEVICE_DFU;
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};
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return BOOT_DEVICE_RAM;
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}
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static u32 __get_primary_bootmedia(u32 devstat)
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{
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u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
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MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
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u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
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MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
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switch (bootmode) {
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case BOOT_DEVICE_OSPI:
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fallthrough;
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case BOOT_DEVICE_QSPI:
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fallthrough;
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case BOOT_DEVICE_XSPI:
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fallthrough;
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case BOOT_DEVICE_SPI:
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return BOOT_DEVICE_SPI;
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case BOOT_DEVICE_ETHERNET_RGMII:
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fallthrough;
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case BOOT_DEVICE_ETHERNET_RMII:
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return BOOT_DEVICE_ETHERNET;
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case BOOT_DEVICE_EMMC:
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return BOOT_DEVICE_MMC1;
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case BOOT_DEVICE_MMC:
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if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
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MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
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return BOOT_DEVICE_MMC2;
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return BOOT_DEVICE_MMC1;
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case BOOT_DEVICE_DFU:
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if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
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MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
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return BOOT_DEVICE_USB;
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return BOOT_DEVICE_DFU;
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case BOOT_DEVICE_NOBOOT:
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return BOOT_DEVICE_RAM;
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}
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return bootmode;
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}
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u32 spl_boot_device(void)
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{
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u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
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u32 bootmedia;
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if (bootindex == K3_PRIMARY_BOOTMODE)
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bootmedia = __get_primary_bootmedia(devstat);
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else
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bootmedia = __get_backup_bootmedia(devstat);
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debug("am625_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
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__func__, devstat, bootmedia, bootindex);
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return bootmedia;
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}
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