mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
e0ece17304
get_board_rev() is not actually providing the board revision. It just returns the CPU revision instead. As the CPU revision is already printed on boot, there is no reason to have get_board_rev(), so let's remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
521 lines
12 KiB
C
521 lines
12 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <mmc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../common/pfuze.h"
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#include <i2c.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/arch/crm_regs.h>
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#include <usb/ehci-fsl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
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#ifdef CONFIG_SYS_I2C_MXC
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1 for PMIC */
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
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.gp = IMX_GPIO_NR(4, 8),
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},
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.sda = {
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.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
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.gp = IMX_GPIO_NR(4, 9),
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},
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};
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#endif
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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static iomux_v3_cfg_t const wdog_pads[] = {
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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
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MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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#define IOX_SDI IMX_GPIO_NR(1, 9)
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#define IOX_STCP IMX_GPIO_NR(1, 12)
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#define IOX_SHCP IMX_GPIO_NR(1, 13)
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static iomux_v3_cfg_t const iox_pads[] = {
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/* IOX_SDI */
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MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* IOX_STCP */
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MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* IOX_SHCP */
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MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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/*
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* PCIE_DIS_B --> Q0
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* PCIE_RST_B --> Q1
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* HDMI_RST_B --> Q2
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* PERI_RST_B --> Q3
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* SENSOR_RST_B --> Q4
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* ENET_RST_B --> Q5
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* PERI_3V3_EN --> Q6
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* LCD_PWR_EN --> Q7
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*/
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enum qn {
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PCIE_DIS_B,
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PCIE_RST_B,
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HDMI_RST_B,
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PERI_RST_B,
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SENSOR_RST_B,
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ENET_RST_B,
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PERI_3V3_EN,
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LCD_PWR_EN,
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};
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enum qn_func {
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qn_reset,
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qn_enable,
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qn_disable,
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};
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enum qn_level {
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qn_low = 0,
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qn_high = 1,
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};
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static enum qn_level seq[3][2] = {
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{0, 1}, {1, 1}, {0, 0}
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};
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static enum qn_func qn_output[8] = {
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qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
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qn_enable
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};
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static void iox74lv_init(void)
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{
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int i;
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for (i = 7; i >= 0; i--) {
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gpio_direction_output(IOX_SHCP, 0);
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
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udelay(500);
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gpio_direction_output(IOX_SHCP, 1);
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udelay(500);
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}
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gpio_direction_output(IOX_STCP, 0);
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udelay(500);
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/*
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* shift register will be output to pins
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*/
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gpio_direction_output(IOX_STCP, 1);
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for (i = 7; i >= 0; i--) {
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gpio_direction_output(IOX_SHCP, 0);
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
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udelay(500);
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gpio_direction_output(IOX_SHCP, 1);
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udelay(500);
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}
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gpio_direction_output(IOX_STCP, 0);
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udelay(500);
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/*
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* shift register will be output to pins
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*/
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gpio_direction_output(IOX_STCP, 1);
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};
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#ifdef CONFIG_FEC_MXC
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
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MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
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};
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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}
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#endif
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
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#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
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#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
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static struct fsl_esdhc_cfg usdhc_cfg[3] = {
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{USDHC1_BASE_ADDR, 0, 4},
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{USDHC3_BASE_ADDR},
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};
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static int mmc_get_env_devno(void)
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{
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struct bootrom_sw_info **p =
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(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
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u8 boot_type = (*p)->boot_dev_type;
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u8 dev_no = (*p)->boot_dev_instance;
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/* If not boot from sd/mmc, use default value */
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if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
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return CONFIG_SYS_MMC_ENV_DEV;
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if (dev_no == 2)
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dev_no--;
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return dev_no;
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}
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static int mmc_map_to_kernel_blk(int dev_no)
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{
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if (dev_no == 1)
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dev_no++;
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return dev_no;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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case USDHC3_BASE_ADDR:
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ret = 1; /* Assume uSDHC3 emmc is always present */
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-boot device node) (Physical Port)
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* mmc0 USDHC1
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* mmc2 USDHC3 (eMMC)
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(
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usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
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gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
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gpio_direction_input(USDHC1_CD_GPIO);
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gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
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gpio_direction_output(USDHC1_PWR_GPIO, 0);
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udelay(500);
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gpio_direction_output(USDHC1_PWR_GPIO, 1);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(
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usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
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gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
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gpio_direction_output(USDHC3_PWR_GPIO, 0);
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udelay(500);
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gpio_direction_output(USDHC3_PWR_GPIO, 1);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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break;
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default:
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printf("Warning: you configured more USDHC controllers"
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"(%d) than supported by the board\n", i + 1);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int check_mmc_autodetect(void)
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{
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char *autodetect_str = getenv("mmcautodetect");
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if ((autodetect_str != NULL) &&
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(strcmp(autodetect_str, "yes") == 0)) {
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return 1;
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}
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return 0;
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}
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static void mmc_late_init(void)
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{
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char cmd[32];
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char mmcblk[32];
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u32 dev_no = mmc_get_env_devno();
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if (!check_mmc_autodetect())
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return;
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setenv_ulong("mmcdev", dev_no);
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/* Set mmcblk env */
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sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
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mmc_map_to_kernel_blk(dev_no));
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setenv("mmcroot", mmcblk);
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sprintf(cmd, "mmc dev %d", dev_no);
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run_command(cmd, 0);
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}
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#endif
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#ifdef CONFIG_FEC_MXC
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int board_eth_init(bd_t *bis)
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{
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int ret;
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setup_iomux_fec();
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ret = fecmxc_initialize_multi(bis, 0,
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CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
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if (ret)
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printf("FEC1 MXC: %s:failed\n", __func__);
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return ret;
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}
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
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= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
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/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
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clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
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(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
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IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
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return set_clk_enet(ENET_125MHz);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
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iox74lv_init();
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#ifdef CONFIG_FEC_MXC
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setup_fec();
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#endif
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
|
|
/* 4 bit bus width */
|
|
{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
|
|
{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
|
|
{NULL, 0},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_POWER
|
|
#define I2C_PMIC 0
|
|
int power_init_board(void)
|
|
{
|
|
struct pmic *p;
|
|
int ret;
|
|
unsigned int reg, rev_id;
|
|
|
|
ret = power_pfuze3000_init(I2C_PMIC);
|
|
if (ret)
|
|
return ret;
|
|
|
|
p = pmic_get("PFUZE3000");
|
|
ret = pmic_probe(p);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
|
|
pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
|
|
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
|
|
|
|
/* disable Low Power Mode during standby mode */
|
|
pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
|
|
reg |= 0x1;
|
|
pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_late_init(void)
|
|
{
|
|
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
add_board_boot_modes(board_boot_modes);
|
|
#endif
|
|
|
|
#ifdef CONFIG_ENV_IS_IN_MMC
|
|
mmc_late_init();
|
|
#endif
|
|
|
|
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
|
|
|
set_wdog_reset(wdog);
|
|
|
|
/*
|
|
* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
|
|
* since we use PMIC_PWRON to reset the board.
|
|
*/
|
|
clrsetbits_le16(&wdog->wcr, 0, 0x10);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: i.MX7D SABRESD\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_USB_EHCI_MX7
|
|
static iomux_v3_cfg_t const usb_otg1_pads[] = {
|
|
MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const usb_otg2_pads[] = {
|
|
MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
int board_ehci_hcd_init(int port)
|
|
{
|
|
switch (port) {
|
|
case 0:
|
|
imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
|
|
ARRAY_SIZE(usb_otg1_pads));
|
|
break;
|
|
case 1:
|
|
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
|
|
ARRAY_SIZE(usb_otg2_pads));
|
|
break;
|
|
default:
|
|
printf("MXC USB port %d not yet supported\n", port);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
#endif
|