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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
279 lines
5.9 KiB
C
279 lines
5.9 KiB
C
/*
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* (C) Copyright 2000, 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* ehnus: change pll frequency.
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* Wed Sep 5 11:45:17 CST 2007
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* hsun@udtech.com.cn
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*/
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#include <common.h>
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#include <config.h>
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#include <command.h>
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#include <i2c.h>
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#ifdef CONFIG_CMD_EEPROM
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#define EEPROM_CONF_OFFSET 0
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#define EEPROM_TEST_OFFSET 16
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#define EEPROM_SDSTP_PARAM 16
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#define PLL_NAME_MAX 12
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#define BUF_STEP 8
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/* eeprom_wirtes 8Byte per op. */
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#define EEPROM_ALTER_FREQ(freq) \
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do { \
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int __i; \
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for (__i = 0; __i < 2; __i++) \
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eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \
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EEPROM_CONF_OFFSET + __i*BUF_STEP, \
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pll_select[freq], \
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BUF_STEP + __i*BUF_STEP); \
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} while (0)
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#define PDEBUG
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#ifdef PDEBUG
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#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET)
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#else
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#define PLL_DEBUG
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#endif
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typedef enum {
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PLL_ebc20,
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PLL_333,
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PLL_4001,
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PLL_4002,
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PLL_533,
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PLL_600,
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PLL_666, /* For now, kilauea can't support */
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RCONF,
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WTEST,
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PLL_TOTAL
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} pll_freq_t;
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static const char
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pll_name[][PLL_NAME_MAX] = {
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"PLL_ebc20",
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"PLL_333",
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"PLL_400@1",
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"PLL_400@2",
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"PLL_533",
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"PLL_600",
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"PLL_666",
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"RCONF",
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"WTEST",
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""
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};
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/*
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* ehnus:
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*/
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static uchar
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pll_select[][EEPROM_SDSTP_PARAM] = {
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/* 0: CPU 333MHz EBC 20MHz, for test only */
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{
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0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 0: 333 */
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{
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0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 1: 400_266 */
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{
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0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 2: 400 */
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{
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0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 3: 533 */
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{
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0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 4: 600 */
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{
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0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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/* 5: 666 */
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{
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0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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},
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{}
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};
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static uchar
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testbuf[EEPROM_SDSTP_PARAM] = {
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0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
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0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
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};
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static void
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pll_debug(int off)
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{
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int i;
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uchar buffer[EEPROM_SDSTP_PARAM];
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memset(buffer, 0, sizeof(buffer));
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eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
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buffer, EEPROM_SDSTP_PARAM);
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printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
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for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
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printf("%02x ", buffer[i]);
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printf("\n");
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}
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static void
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test_write(void)
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{
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printf("Debug: test eeprom_write ... ");
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/*
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* Write twice, 8 bytes per write
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*/
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eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
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testbuf, 8);
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eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
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testbuf, 16);
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printf("done\n");
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pll_debug(EEPROM_TEST_OFFSET);
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}
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int
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do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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char c = '\0';
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pll_freq_t pll_freq;
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if (argc < 2)
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return cmd_usage(cmdtp);
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for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) {
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if (!strcmp(pll_name[pll_freq], argv[1]))
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break;
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}
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switch (pll_freq) {
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case PLL_ebc20:
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case PLL_333:
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case PLL_4001:
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case PLL_4002:
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case PLL_533:
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case PLL_600:
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EEPROM_ALTER_FREQ(pll_freq);
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break;
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case PLL_666: /* not support */
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printf("Choose this option will result in a boot failure."
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"\nContinue? (Y/N): ");
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c = getc(); putc('\n');
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if ((c == 'y') || (c == 'Y')) {
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EEPROM_ALTER_FREQ(pll_freq);
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break;
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}
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goto ret;
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case RCONF:
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pll_debug(EEPROM_CONF_OFFSET);
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goto ret;
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case WTEST:
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printf("DEBUG: write test\n");
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test_write();
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goto ret;
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default:
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printf("Invalid options\n\n");
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return cmd_usage(cmdtp);
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}
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printf("PLL set to %s, "
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"reset the board to take effect\n", pll_name[pll_freq]);
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PLL_DEBUG;
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ret:
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return 0;
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}
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U_BOOT_CMD(
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pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter,
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"change pll frequence",
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"pllalter <selection> - change pll frequence \n\n\
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** New freq take effect after reset. ** \n\
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----------------------------------------------\n\
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PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
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\t Same as PLL_333 \n\
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\t except \n\
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\t EBC: 20 MHz \n\
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----------------------------------------------\n\
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PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 666 MHz \n\
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\t CPU: 333 MHz \n\
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\t PLB: 166 MHz \n\
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\t OPB: 83 MHz \n\
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\t DDR: 83 MHz \n\
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------------------------------------------------\n\
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PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 800 MHz \n\
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\t CPU: 400 MHz \n\
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\t PLB: 133 MHz \n\
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\t OPB: 66 MHz \n\
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\t DDR: 133 MHz \n\
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------------------------------------------------\n\
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PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 800 MHz \n\
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\t CPU: 400 MHz \n\
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\t PLB: 200 MHz \n\
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\t OPB: 100 MHz \n\
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\t DDR: 200 MHz \n\
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----------------------------------------------\n\
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PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 1066 MHz \n\
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\t CPU: 533 MHz \n\
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\t PLB: 177 MHz \n\
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\t OPB: 88 MHz \n\
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\t DDR: 177 MHz \n\
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----------------------------------------------\n\
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PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 1200 MHz \n\
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\t CPU: 600 MHz \n\
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\t PLB: 200 MHz \n\
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\t OPB: 100 MHz \n\
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\t DDR: 200 MHz \n\
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----------------------------------------------\n\
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PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
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\t VCO: 1333 MHz \n\
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\t CPU: 666 MHz \n\
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\t PLB: 166 MHz \n\
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\t OPB: 83 MHz \n\
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\t DDR: 166 MHz \n\
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-----------------------------------------------\n\
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RCONF: Read current eeprom configuration. \n\
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-----------------------------------------------\n\
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WTEST: Test EEPROM write with predefined values\n\
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-----------------------------------------------"
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);
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#endif /* CONFIG_CMD_EEPROM */
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