mirror of
https://github.com/AsahiLinux/u-boot
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4f6c810106
When doing the AT91CAP9/AT91SAM9 port, a number of header files were copied from the Linux kernel sources. This patch explicitly specifies this origin for all the copied headers, and for those missing copyright information, adds it. Additionaly, the header file 'at91sam926x_mc.h' has been superceeded in the latest kernel sources by 'at91sam9_smc.h'. The copyright information has been confirmed by the AT91 Linux kernel maintainer, Andrew Victor <avictor.za@gmail.com>. Signed-off-by: Stelian Pop <stelian@popies.net> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
366 lines
12 KiB
C
366 lines
12 KiB
C
/*
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* [origin: Linux kernel include/asm-arm/arch-at91/gpio.h]
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*
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* Copyright (C) 2005 HP Labs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __ASM_ARCH_AT91_GPIO_H
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#define __ASM_ARCH_AT91_GPIO_H
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/at91_pio.h>
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#define PIN_BASE 32
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#define MAX_GPIO_BANKS 5
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/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
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#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
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#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
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#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
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#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
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#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
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#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
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#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
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#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
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#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
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#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
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#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
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#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
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#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
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#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
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#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
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#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
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#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
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#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
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#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
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#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
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#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
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#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
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#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
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#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
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#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
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#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
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#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
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#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
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#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
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#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
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#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
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#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
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#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
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#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
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#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
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#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
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#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
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#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
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#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
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#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
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#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
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#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
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#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
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#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
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#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
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#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
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#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
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#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
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#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
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#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
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#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
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#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
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#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
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#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
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#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
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#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
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#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
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#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
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#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
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#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
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#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
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#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
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#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
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#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
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#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
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#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
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#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
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#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
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#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
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#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
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#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
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#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
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#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
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#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
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#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
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#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
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#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
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#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
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#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
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#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
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#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
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#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
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#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
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#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
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#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
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#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
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#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
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#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
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#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
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#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
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#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
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#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
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#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
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#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
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#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
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#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
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#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0)
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#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1)
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#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2)
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#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3)
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#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4)
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#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5)
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#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6)
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#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7)
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#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8)
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#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9)
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#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10)
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#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11)
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#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12)
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#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13)
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#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14)
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#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15)
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#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16)
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#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17)
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#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18)
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#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19)
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#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20)
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#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21)
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#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22)
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#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23)
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#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24)
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#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25)
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#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26)
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#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27)
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#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28)
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#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29)
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#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30)
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#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31)
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#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0)
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#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1)
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#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2)
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#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3)
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#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4)
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#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5)
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#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6)
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#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7)
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#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8)
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#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9)
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#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10)
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#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11)
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#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12)
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#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13)
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#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14)
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#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15)
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#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16)
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#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17)
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#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18)
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#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19)
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#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20)
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#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21)
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#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22)
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#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23)
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#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24)
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#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25)
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#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26)
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#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27)
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#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28)
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#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29)
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#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30)
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#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31)
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static unsigned long at91_pios[] = {
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AT91_PIOA,
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AT91_PIOB,
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AT91_PIOC,
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#ifdef AT91_PIOD
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AT91_PIOD,
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#ifdef AT91_PIOE
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AT91_PIOE
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#endif
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#endif
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};
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static inline void *pin_to_controller(unsigned pin)
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{
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pin -= PIN_BASE;
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pin /= 32;
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return (void *)(AT91_BASE_SYS + at91_pios[pin]);
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}
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static inline unsigned pin_to_mask(unsigned pin)
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{
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pin -= PIN_BASE;
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return 1 << (pin % 32);
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}
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/*
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* mux the pin to the "GPIO" peripheral role.
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*/
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static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
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{
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void *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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/*
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* mux the pin to the "A" internal peripheral role.
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*/
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static inline int at91_set_A_periph(unsigned pin, int use_pullup)
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{
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void *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_ASR);
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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/*
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* mux the pin to the "B" internal peripheral role.
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*/
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static inline int at91_set_B_periph(unsigned pin, int use_pullup)
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{
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void *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_BSR);
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
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* configure it for an input.
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*/
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static inline int at91_set_gpio_input(unsigned pin, int use_pullup)
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{
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void *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_ODR);
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
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* and configure it for an output.
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*/
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static inline int at91_set_gpio_output(unsigned pin, int value)
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{
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void *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + PIO_PUDR);
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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__raw_writel(mask, pio + PIO_OER);
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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/*
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* enable/disable the glitch filter; mostly used with IRQ handling.
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*/
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static inline int at91_set_deglitch(unsigned pin, int is_on)
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{
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void *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
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return 0;
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}
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/*
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* enable/disable the multi-driver; This is only valid for output and
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* allows the output pin to run as an open collector output.
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*/
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static inline int at91_set_multi_drive(unsigned pin, int is_on)
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{
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void *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
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return 0;
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}
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static inline int gpio_direction_input(unsigned pin)
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{
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void *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!(__raw_readl(pio + PIO_PSR) & mask))
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return -EINVAL;
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__raw_writel(mask, pio + PIO_ODR);
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return 0;
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}
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static inline int gpio_direction_output(unsigned pin, int value)
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{
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void *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!(__raw_readl(pio + PIO_PSR) & mask))
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return -EINVAL;
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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__raw_writel(mask, pio + PIO_OER);
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return 0;
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}
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/*
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* assuming the pin is muxed as a gpio output, set its value.
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*/
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static inline int at91_set_gpio_value(unsigned pin, int value)
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{
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void *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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return 0;
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}
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/*
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* read the pin's value (works even if it's not muxed as a gpio).
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*/
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static inline int at91_get_gpio_value(unsigned pin)
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{
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void *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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u32 pdsr;
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pdsr = __raw_readl(pio + PIO_PDSR);
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return (pdsr & mask) != 0;
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}
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#endif
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