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https://github.com/AsahiLinux/u-boot
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a6ac775bae
MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware strapping. This also has the side effect of running the DDR clock in synchronous mode with the CPU core clock rather than from an independent PLL. We've seen this improve reliability in operation across a number of boards and temperature ranges. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
161 lines
4.1 KiB
C
161 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Allied Telesis Labs
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*/
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#include <common.h>
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#include <command.h>
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#include <dm.h>
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#include <i2c.h>
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#include <asm/gpio.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "../common/gpio_hog.h"
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#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
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#include <../serdes/a38x/high_speed_env_spec.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
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#define CONFIG_NVS_LOCATION 0xf4800000
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#define CONFIG_NVS_SIZE (512 << 10)
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static struct serdes_map board_serdes_map[] = {
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{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
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};
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int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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{
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*serdes_map_array = board_serdes_map;
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*count = ARRAY_SIZE(board_serdes_map);
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return 0;
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}
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/*
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* Define the DDR layout / topology here in the board file. This will
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* be used by the DDR3 init code in the SPL U-Boot version to configure
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* the DDR3 controller.
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*/
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static struct mv_ddr_topology_map board_topology_map = {
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1866M, /* speed_bin */
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MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
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MV_DDR_DIE_CAP_4GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l cas_wl */
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MV_DDR_TEMP_LOW, /* temperature */
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MV_DDR_TIM_2T} }, /* timing */
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BUS_MASK_32BIT_ECC, /* subphys mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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};
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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/* Return the board topology as defined in the board code */
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return &board_topology_map;
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}
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(0x00001111, MVEBU_MPP_BASE + 0x00);
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writel(0x00000000, MVEBU_MPP_BASE + 0x04);
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writel(0x55000000, MVEBU_MPP_BASE + 0x08);
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writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
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writel(0x55555555, MVEBU_MPP_BASE + 0x10);
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writel(0x00100565, MVEBU_MPP_BASE + 0x14);
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writel(0x40000000, MVEBU_MPP_BASE + 0x18);
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writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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/* window for NVS */
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mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
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/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
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writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
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return 0;
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}
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static int led_7seg_init(unsigned int segments)
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{
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int node;
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int ret;
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int i;
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struct gpio_desc desc[8];
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node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
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"atl,of-led-7seg");
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if (node < 0)
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return -ENODEV;
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ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
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"segment-gpios", desc,
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ARRAY_SIZE(desc), GPIOD_IS_OUT);
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if (ret < 0)
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return ret;
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for (i = 0; i < ARRAY_SIZE(desc); i++) {
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ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
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if (ret)
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return ret;
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}
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return 0;
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}
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
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led_en = {};
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gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
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gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
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gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
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gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
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#ifdef MTDPARTS_MTDOOPS
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env_set("mtdoops", MTDPARTS_MTDOOPS);
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#endif
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led_7seg_init(0xff);
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return 0;
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}
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#endif
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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puts("Board: " CONFIG_SYS_BOARD "\n");
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return 0;
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}
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#endif
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