mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 22:33:18 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
1087 lines
26 KiB
C
1087 lines
26 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <div64.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/pcc.h>
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#include <asm/arch/sys_proto.h>
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scg_p scg1_regs = (scg_p)SCG1_RBASE;
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static u32 scg_src_get_rate(enum scg_clk clksrc)
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{
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u32 reg;
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switch (clksrc) {
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case SCG_SOSC_CLK:
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reg = readl(&scg1_regs->sosccsr);
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if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
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return 0;
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return 24000000;
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case SCG_FIRC_CLK:
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reg = readl(&scg1_regs->firccsr);
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if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
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return 0;
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return 48000000;
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case SCG_SIRC_CLK:
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reg = readl(&scg1_regs->sirccsr);
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if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
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return 0;
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return 16000000;
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case SCG_ROSC_CLK:
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reg = readl(&scg1_regs->rtccsr);
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if (!(reg & SCG_ROSC_CSR_ROSCVLD_MASK))
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return 0;
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return 32768;
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default:
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break;
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}
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return 0;
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}
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static u32 scg_sircdiv_get_rate(enum scg_clk clk)
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{
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u32 reg, val, rate;
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u32 shift, mask;
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switch (clk) {
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case SCG_SIRC_DIV1_CLK:
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mask = SCG_SIRCDIV_DIV1_MASK;
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shift = SCG_SIRCDIV_DIV1_SHIFT;
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break;
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case SCG_SIRC_DIV2_CLK:
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mask = SCG_SIRCDIV_DIV2_MASK;
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shift = SCG_SIRCDIV_DIV2_SHIFT;
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break;
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case SCG_SIRC_DIV3_CLK:
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mask = SCG_SIRCDIV_DIV3_MASK;
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shift = SCG_SIRCDIV_DIV3_SHIFT;
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break;
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default:
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return 0;
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}
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reg = readl(&scg1_regs->sirccsr);
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if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
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return 0;
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reg = readl(&scg1_regs->sircdiv);
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val = (reg & mask) >> shift;
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if (!val) /*clock disabled*/
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return 0;
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rate = scg_src_get_rate(SCG_SIRC_CLK);
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rate = rate / (1 << (val - 1));
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return rate;
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}
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static u32 scg_fircdiv_get_rate(enum scg_clk clk)
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{
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u32 reg, val, rate;
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u32 shift, mask;
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switch (clk) {
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case SCG_FIRC_DIV1_CLK:
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mask = SCG_FIRCDIV_DIV1_MASK;
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shift = SCG_FIRCDIV_DIV1_SHIFT;
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break;
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case SCG_FIRC_DIV2_CLK:
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mask = SCG_FIRCDIV_DIV2_MASK;
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shift = SCG_FIRCDIV_DIV2_SHIFT;
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break;
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case SCG_FIRC_DIV3_CLK:
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mask = SCG_FIRCDIV_DIV3_MASK;
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shift = SCG_FIRCDIV_DIV3_SHIFT;
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break;
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default:
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return 0;
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}
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reg = readl(&scg1_regs->firccsr);
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if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
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return 0;
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reg = readl(&scg1_regs->fircdiv);
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val = (reg & mask) >> shift;
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if (!val) /*clock disabled*/
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return 0;
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rate = scg_src_get_rate(SCG_FIRC_CLK);
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rate = rate / (1 << (val - 1));
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return rate;
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}
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static u32 scg_soscdiv_get_rate(enum scg_clk clk)
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{
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u32 reg, val, rate;
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u32 shift, mask;
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switch (clk) {
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case SCG_SOSC_DIV1_CLK:
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mask = SCG_SOSCDIV_DIV1_MASK;
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shift = SCG_SOSCDIV_DIV1_SHIFT;
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break;
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case SCG_SOSC_DIV2_CLK:
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mask = SCG_SOSCDIV_DIV2_MASK;
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shift = SCG_SOSCDIV_DIV2_SHIFT;
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break;
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case SCG_SOSC_DIV3_CLK:
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mask = SCG_SOSCDIV_DIV3_MASK;
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shift = SCG_SOSCDIV_DIV3_SHIFT;
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break;
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default:
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return 0;
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}
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reg = readl(&scg1_regs->sosccsr);
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if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
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return 0;
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reg = readl(&scg1_regs->soscdiv);
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val = (reg & mask) >> shift;
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if (!val) /*clock disabled*/
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return 0;
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rate = scg_src_get_rate(SCG_SOSC_CLK);
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rate = rate / (1 << (val - 1));
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return rate;
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}
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static u32 scg_apll_pfd_get_rate(enum scg_clk clk)
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{
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u32 reg, val, rate;
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u32 shift, mask, gate, valid;
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switch (clk) {
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case SCG_APLL_PFD0_CLK:
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gate = SCG_PLL_PFD0_GATE_MASK;
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valid = SCG_PLL_PFD0_VALID_MASK;
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mask = SCG_PLL_PFD0_FRAC_MASK;
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shift = SCG_PLL_PFD0_FRAC_SHIFT;
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break;
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case SCG_APLL_PFD1_CLK:
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gate = SCG_PLL_PFD1_GATE_MASK;
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valid = SCG_PLL_PFD1_VALID_MASK;
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mask = SCG_PLL_PFD1_FRAC_MASK;
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shift = SCG_PLL_PFD1_FRAC_SHIFT;
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break;
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case SCG_APLL_PFD2_CLK:
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gate = SCG_PLL_PFD2_GATE_MASK;
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valid = SCG_PLL_PFD2_VALID_MASK;
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mask = SCG_PLL_PFD2_FRAC_MASK;
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shift = SCG_PLL_PFD2_FRAC_SHIFT;
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break;
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case SCG_APLL_PFD3_CLK:
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gate = SCG_PLL_PFD3_GATE_MASK;
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valid = SCG_PLL_PFD3_VALID_MASK;
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mask = SCG_PLL_PFD3_FRAC_MASK;
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shift = SCG_PLL_PFD3_FRAC_SHIFT;
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break;
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default:
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return 0;
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}
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reg = readl(&scg1_regs->apllpfd);
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if (reg & gate || !(reg & valid))
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return 0;
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clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg);
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val = (reg & mask) >> shift;
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rate = decode_pll(PLL_A7_APLL);
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rate = rate / val * 18;
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clk_debug("scg_apll_pfd_get_rate rate %u\n", rate);
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return rate;
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}
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static u32 scg_spll_pfd_get_rate(enum scg_clk clk)
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{
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u32 reg, val, rate;
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u32 shift, mask, gate, valid;
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switch (clk) {
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case SCG_SPLL_PFD0_CLK:
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gate = SCG_PLL_PFD0_GATE_MASK;
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valid = SCG_PLL_PFD0_VALID_MASK;
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mask = SCG_PLL_PFD0_FRAC_MASK;
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shift = SCG_PLL_PFD0_FRAC_SHIFT;
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break;
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case SCG_SPLL_PFD1_CLK:
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gate = SCG_PLL_PFD1_GATE_MASK;
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valid = SCG_PLL_PFD1_VALID_MASK;
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mask = SCG_PLL_PFD1_FRAC_MASK;
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shift = SCG_PLL_PFD1_FRAC_SHIFT;
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break;
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case SCG_SPLL_PFD2_CLK:
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gate = SCG_PLL_PFD2_GATE_MASK;
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valid = SCG_PLL_PFD2_VALID_MASK;
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mask = SCG_PLL_PFD2_FRAC_MASK;
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shift = SCG_PLL_PFD2_FRAC_SHIFT;
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break;
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case SCG_SPLL_PFD3_CLK:
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gate = SCG_PLL_PFD3_GATE_MASK;
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valid = SCG_PLL_PFD3_VALID_MASK;
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mask = SCG_PLL_PFD3_FRAC_MASK;
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shift = SCG_PLL_PFD3_FRAC_SHIFT;
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break;
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default:
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return 0;
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}
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reg = readl(&scg1_regs->spllpfd);
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if (reg & gate || !(reg & valid))
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return 0;
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clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg);
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val = (reg & mask) >> shift;
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rate = decode_pll(PLL_A7_SPLL);
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rate = rate / val * 18;
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clk_debug("scg_spll_pfd_get_rate rate %u\n", rate);
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return rate;
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}
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static u32 scg_apll_get_rate(void)
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{
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u32 reg, val, rate;
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reg = readl(&scg1_regs->apllcfg);
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val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
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if (!val) {
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/* APLL clock after two dividers */
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rate = decode_pll(PLL_A7_APLL);
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val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
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SCG_PLL_CFG_POSTDIV1_SHIFT;
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rate = rate / (val + 1);
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val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
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SCG_PLL_CFG_POSTDIV2_SHIFT;
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rate = rate / (val + 1);
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} else {
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/* APLL PFD clock */
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val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
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SCG_PLL_CFG_PFDSEL_SHIFT;
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rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
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}
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return rate;
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}
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static u32 scg_spll_get_rate(void)
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{
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u32 reg, val, rate;
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reg = readl(&scg1_regs->spllcfg);
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val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
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clk_debug("scg_spll_get_rate reg 0x%x\n", reg);
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if (!val) {
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/* APLL clock after two dividers */
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rate = decode_pll(PLL_A7_SPLL);
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val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
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SCG_PLL_CFG_POSTDIV1_SHIFT;
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rate = rate / (val + 1);
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val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
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SCG_PLL_CFG_POSTDIV2_SHIFT;
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rate = rate / (val + 1);
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clk_debug("scg_spll_get_rate SPLL %u\n", rate);
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} else {
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/* APLL PFD clock */
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val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
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SCG_PLL_CFG_PFDSEL_SHIFT;
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rate = scg_spll_pfd_get_rate(SCG_SPLL_PFD0_CLK + val);
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clk_debug("scg_spll_get_rate PFD %u\n", rate);
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}
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return rate;
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}
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static u32 scg_ddr_get_rate(void)
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{
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u32 reg, val, rate, div;
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reg = readl(&scg1_regs->ddrccr);
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val = (reg & SCG_DDRCCR_DDRCS_MASK) >> SCG_DDRCCR_DDRCS_SHIFT;
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div = (reg & SCG_DDRCCR_DDRDIV_MASK) >> SCG_DDRCCR_DDRDIV_SHIFT;
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if (!div)
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return 0;
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if (!val) {
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reg = readl(&scg1_regs->apllcfg);
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val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
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SCG_PLL_CFG_PFDSEL_SHIFT;
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rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
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} else {
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rate = decode_pll(PLL_USB);
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}
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rate = rate / (1 << (div - 1));
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return rate;
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}
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static u32 scg_nic_get_rate(enum scg_clk clk)
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{
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u32 reg, val, rate;
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u32 shift, mask;
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reg = readl(&scg1_regs->niccsr);
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val = (reg & SCG_NICCSR_NICCS_MASK) >> SCG_NICCSR_NICCS_SHIFT;
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clk_debug("scg_nic_get_rate niccsr 0x%x\n", reg);
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if (!val)
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rate = scg_src_get_rate(SCG_FIRC_CLK);
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else
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rate = scg_ddr_get_rate();
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clk_debug("scg_nic_get_rate parent rate %u\n", rate);
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val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT;
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rate = rate / (val + 1);
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clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate);
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switch (clk) {
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case SCG_NIC0_CLK:
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return rate;
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case SCG_GPU_CLK:
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mask = SCG_NICCSR_GPUDIV_MASK;
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shift = SCG_NICCSR_GPUDIV_SHIFT;
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break;
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case SCG_NIC1_EXT_CLK:
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case SCG_NIC1_BUS_CLK:
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case SCG_NIC1_CLK:
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mask = SCG_NICCSR_NIC1DIV_MASK;
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shift = SCG_NICCSR_NIC1DIV_SHIFT;
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break;
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default:
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return 0;
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}
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val = (reg & mask) >> shift;
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rate = rate / (val + 1);
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clk_debug("scg_nic_get_rate NIC1 rate %u\n", rate);
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switch (clk) {
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case SCG_GPU_CLK:
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case SCG_NIC1_CLK:
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return rate;
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case SCG_NIC1_EXT_CLK:
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mask = SCG_NICCSR_NIC1EXTDIV_MASK;
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shift = SCG_NICCSR_NIC1EXTDIV_SHIFT;
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break;
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case SCG_NIC1_BUS_CLK:
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mask = SCG_NICCSR_NIC1BUSDIV_MASK;
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shift = SCG_NICCSR_NIC1BUSDIV_SHIFT;
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break;
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default:
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return 0;
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}
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val = (reg & mask) >> shift;
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rate = rate / (val + 1);
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clk_debug("scg_nic_get_rate NIC1 bus rate %u\n", rate);
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return rate;
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}
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static enum scg_clk scg_scs_array[4] = {
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SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK,
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};
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static u32 scg_sys_get_rate(enum scg_clk clk)
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{
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u32 reg, val, rate;
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if (clk != SCG_CORE_CLK && clk != SCG_BUS_CLK)
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return 0;
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reg = readl(&scg1_regs->csr);
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val = (reg & SCG_CCR_SCS_MASK) >> SCG_CCR_SCS_SHIFT;
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clk_debug("scg_sys_get_rate reg 0x%x\n", reg);
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switch (val) {
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case SCG_SCS_SYS_OSC:
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case SCG_SCS_SLOW_IRC:
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case SCG_SCS_FAST_IRC:
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case SCG_SCS_RTC_OSC:
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rate = scg_src_get_rate(scg_scs_array[val]);
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break;
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case 5:
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rate = scg_apll_get_rate();
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break;
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case 6:
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rate = scg_spll_get_rate();
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break;
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default:
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return 0;
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}
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clk_debug("scg_sys_get_rate parent rate %u\n", rate);
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val = (reg & SCG_CCR_DIVCORE_MASK) >> SCG_CCR_DIVCORE_SHIFT;
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rate = rate / (val + 1);
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if (clk == SCG_BUS_CLK) {
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val = (reg & SCG_CCR_DIVBUS_MASK) >> SCG_CCR_DIVBUS_SHIFT;
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rate = rate / (val + 1);
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}
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return rate;
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}
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u32 decode_pll(enum pll_clocks pll)
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{
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u32 reg, pre_div, infreq, mult;
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u32 num, denom;
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/*
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* Alought there are four choices for the bypass src,
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* we choose OSC_24M which is the default set in ROM.
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*/
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switch (pll) {
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case PLL_A7_SPLL:
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reg = readl(&scg1_regs->spllcsr);
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if (!(reg & SCG_SPLL_CSR_SPLLVLD_MASK))
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return 0;
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reg = readl(&scg1_regs->spllcfg);
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pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
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SCG_PLL_CFG_PREDIV_SHIFT;
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pre_div += 1;
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|
|
|
mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >>
|
|
SCG_PLL_CFG_MULT_SHIFT;
|
|
|
|
infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
|
|
SCG_PLL_CFG_CLKSRC_SHIFT;
|
|
if (!infreq)
|
|
infreq = scg_src_get_rate(SCG_SOSC_CLK);
|
|
else
|
|
infreq = scg_src_get_rate(SCG_FIRC_CLK);
|
|
|
|
num = readl(&scg1_regs->spllnum);
|
|
denom = readl(&scg1_regs->splldenom);
|
|
|
|
infreq = infreq / pre_div;
|
|
|
|
return infreq * mult + infreq * num / denom;
|
|
|
|
case PLL_A7_APLL:
|
|
reg = readl(&scg1_regs->apllcsr);
|
|
|
|
if (!(reg & SCG_APLL_CSR_APLLVLD_MASK))
|
|
return 0;
|
|
|
|
reg = readl(&scg1_regs->apllcfg);
|
|
|
|
pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
|
|
SCG_PLL_CFG_PREDIV_SHIFT;
|
|
pre_div += 1;
|
|
|
|
mult = (reg & SCG_APLL_CFG_MULT_MASK) >>
|
|
SCG_PLL_CFG_MULT_SHIFT;
|
|
|
|
infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
|
|
SCG_PLL_CFG_CLKSRC_SHIFT;
|
|
if (!infreq)
|
|
infreq = scg_src_get_rate(SCG_SOSC_CLK);
|
|
else
|
|
infreq = scg_src_get_rate(SCG_FIRC_CLK);
|
|
|
|
num = readl(&scg1_regs->apllnum);
|
|
denom = readl(&scg1_regs->aplldenom);
|
|
|
|
infreq = infreq / pre_div;
|
|
|
|
return infreq * mult + infreq * num / denom;
|
|
|
|
case PLL_USB:
|
|
reg = readl(&scg1_regs->upllcsr);
|
|
|
|
if (!(reg & SCG_UPLL_CSR_UPLLVLD_MASK))
|
|
return 0;
|
|
|
|
return 480000000u;
|
|
|
|
case PLL_MIPI:
|
|
return 480000000u;
|
|
default:
|
|
printf("Unsupported pll clocks %d\n", pll);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
u32 scg_clk_get_rate(enum scg_clk clk)
|
|
{
|
|
switch (clk) {
|
|
case SCG_SIRC_DIV1_CLK:
|
|
case SCG_SIRC_DIV2_CLK:
|
|
case SCG_SIRC_DIV3_CLK:
|
|
return scg_sircdiv_get_rate(clk);
|
|
|
|
case SCG_FIRC_DIV1_CLK:
|
|
case SCG_FIRC_DIV2_CLK:
|
|
case SCG_FIRC_DIV3_CLK:
|
|
return scg_fircdiv_get_rate(clk);
|
|
|
|
case SCG_SOSC_DIV1_CLK:
|
|
case SCG_SOSC_DIV2_CLK:
|
|
case SCG_SOSC_DIV3_CLK:
|
|
return scg_soscdiv_get_rate(clk);
|
|
|
|
case SCG_CORE_CLK:
|
|
case SCG_BUS_CLK:
|
|
return scg_sys_get_rate(clk);
|
|
|
|
case SCG_SPLL_PFD0_CLK:
|
|
case SCG_SPLL_PFD1_CLK:
|
|
case SCG_SPLL_PFD2_CLK:
|
|
case SCG_SPLL_PFD3_CLK:
|
|
return scg_spll_pfd_get_rate(clk);
|
|
|
|
case SCG_APLL_PFD0_CLK:
|
|
case SCG_APLL_PFD1_CLK:
|
|
case SCG_APLL_PFD2_CLK:
|
|
case SCG_APLL_PFD3_CLK:
|
|
return scg_apll_pfd_get_rate(clk);
|
|
|
|
case SCG_DDR_CLK:
|
|
return scg_ddr_get_rate();
|
|
|
|
case SCG_NIC0_CLK:
|
|
case SCG_GPU_CLK:
|
|
case SCG_NIC1_CLK:
|
|
case SCG_NIC1_BUS_CLK:
|
|
case SCG_NIC1_EXT_CLK:
|
|
return scg_nic_get_rate(clk);
|
|
|
|
case USB_PLL_OUT:
|
|
return decode_pll(PLL_USB);
|
|
|
|
case MIPI_PLL_OUT:
|
|
return decode_pll(PLL_MIPI);
|
|
|
|
case SCG_SOSC_CLK:
|
|
case SCG_FIRC_CLK:
|
|
case SCG_SIRC_CLK:
|
|
case SCG_ROSC_CLK:
|
|
return scg_src_get_rate(clk);
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
int scg_enable_pll_pfd(enum scg_clk clk, u32 frac)
|
|
{
|
|
u32 reg;
|
|
u32 shift, mask, gate, valid;
|
|
u32 addr;
|
|
|
|
if (frac < 12 || frac > 35)
|
|
return -EINVAL;
|
|
|
|
switch (clk) {
|
|
case SCG_SPLL_PFD0_CLK:
|
|
case SCG_APLL_PFD0_CLK:
|
|
gate = SCG_PLL_PFD0_GATE_MASK;
|
|
valid = SCG_PLL_PFD0_VALID_MASK;
|
|
mask = SCG_PLL_PFD0_FRAC_MASK;
|
|
shift = SCG_PLL_PFD0_FRAC_SHIFT;
|
|
|
|
if (clk == SCG_SPLL_PFD0_CLK)
|
|
addr = (u32)(&scg1_regs->spllpfd);
|
|
else
|
|
addr = (u32)(&scg1_regs->apllpfd);
|
|
break;
|
|
case SCG_SPLL_PFD1_CLK:
|
|
case SCG_APLL_PFD1_CLK:
|
|
gate = SCG_PLL_PFD1_GATE_MASK;
|
|
valid = SCG_PLL_PFD1_VALID_MASK;
|
|
mask = SCG_PLL_PFD1_FRAC_MASK;
|
|
shift = SCG_PLL_PFD1_FRAC_SHIFT;
|
|
|
|
if (clk == SCG_SPLL_PFD1_CLK)
|
|
addr = (u32)(&scg1_regs->spllpfd);
|
|
else
|
|
addr = (u32)(&scg1_regs->apllpfd);
|
|
break;
|
|
case SCG_SPLL_PFD2_CLK:
|
|
case SCG_APLL_PFD2_CLK:
|
|
gate = SCG_PLL_PFD2_GATE_MASK;
|
|
valid = SCG_PLL_PFD2_VALID_MASK;
|
|
mask = SCG_PLL_PFD2_FRAC_MASK;
|
|
shift = SCG_PLL_PFD2_FRAC_SHIFT;
|
|
|
|
if (clk == SCG_SPLL_PFD2_CLK)
|
|
addr = (u32)(&scg1_regs->spllpfd);
|
|
else
|
|
addr = (u32)(&scg1_regs->apllpfd);
|
|
break;
|
|
case SCG_SPLL_PFD3_CLK:
|
|
case SCG_APLL_PFD3_CLK:
|
|
gate = SCG_PLL_PFD3_GATE_MASK;
|
|
valid = SCG_PLL_PFD3_VALID_MASK;
|
|
mask = SCG_PLL_PFD3_FRAC_MASK;
|
|
shift = SCG_PLL_PFD3_FRAC_SHIFT;
|
|
|
|
if (clk == SCG_SPLL_PFD3_CLK)
|
|
addr = (u32)(&scg1_regs->spllpfd);
|
|
else
|
|
addr = (u32)(&scg1_regs->apllpfd);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Gate the PFD */
|
|
reg = readl(addr);
|
|
reg |= gate;
|
|
writel(reg, addr);
|
|
|
|
/* Write Frac divider */
|
|
reg &= ~mask;
|
|
reg |= (frac << shift) & mask;
|
|
writel(reg, addr);
|
|
|
|
/*
|
|
* Un-gate the PFD
|
|
* (Need un-gate before checking valid, not align with RM)
|
|
*/
|
|
reg &= ~gate;
|
|
writel(reg, addr);
|
|
|
|
/* Wait for PFD clock being valid */
|
|
do {
|
|
reg = readl(addr);
|
|
} while (!(reg & valid));
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2)
|
|
int scg_enable_usb_pll(bool usb_control)
|
|
{
|
|
u32 sosc_rate;
|
|
s32 timeout = 1000000;
|
|
u32 reg;
|
|
|
|
struct usbphy_regs *usbphy =
|
|
(struct usbphy_regs *)USBPHY_RBASE;
|
|
|
|
sosc_rate = scg_src_get_rate(SCG_SOSC_CLK);
|
|
if (!sosc_rate)
|
|
return -EPERM;
|
|
|
|
reg = readl(SIM0_RBASE + 0x3C);
|
|
if (usb_control)
|
|
reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
|
|
else
|
|
reg |= SIM_MISC_CTRL0_USB_PLL_EN_MASK;
|
|
writel(reg, SIM0_RBASE + 0x3C);
|
|
|
|
if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {
|
|
writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr);
|
|
|
|
switch (sosc_rate) {
|
|
case 24000000:
|
|
writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
|
|
break;
|
|
|
|
case 30000000:
|
|
writel(0x800000, &usbphy->usb1_pll_480_ctrl_set);
|
|
break;
|
|
|
|
case 19200000:
|
|
writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set);
|
|
break;
|
|
|
|
default:
|
|
writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
|
|
break;
|
|
}
|
|
|
|
/* Enable the regulator first */
|
|
writel(PLL_USB_REG_ENABLE_MASK,
|
|
&usbphy->usb1_pll_480_ctrl_set);
|
|
|
|
/* Wait at least 15us */
|
|
udelay(15);
|
|
|
|
/* Enable the power */
|
|
writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set);
|
|
|
|
/* Wait lock */
|
|
while (timeout--) {
|
|
if (readl(&usbphy->usb1_pll_480_ctrl) &
|
|
PLL_USB_LOCK_MASK)
|
|
break;
|
|
}
|
|
|
|
if (timeout <= 0) {
|
|
/* If timeout, we power down the pll */
|
|
writel(PLL_USB_PWR_MASK,
|
|
&usbphy->usb1_pll_480_ctrl_clr);
|
|
return -ETIME;
|
|
}
|
|
}
|
|
|
|
/* Clear the bypass */
|
|
writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr);
|
|
|
|
/* Enable the PLL clock out to USB */
|
|
writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK),
|
|
&usbphy->usb1_pll_480_ctrl_set);
|
|
|
|
if (!usb_control) {
|
|
while (timeout--) {
|
|
if (readl(&scg1_regs->upllcsr) &
|
|
SCG_UPLL_CSR_UPLLVLD_MASK)
|
|
break;
|
|
}
|
|
|
|
if (timeout <= 0) {
|
|
reg = readl(SIM0_RBASE + 0x3C);
|
|
reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
|
|
writel(reg, SIM0_RBASE + 0x3C);
|
|
return -ETIME;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* A7 domain system clock source is SPLL */
|
|
#define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT)
|
|
|
|
/* A7 Core clck = SPLL PFD0 / 1 = 500MHz / 1 = 500MHz */
|
|
#define SCG1_RCCR_DIVCORE_NUM ((0x0) << SCG_CCR_DIVCORE_SHIFT)
|
|
#define SCG1_RCCR_CFG_MASK (SCG_CCR_SCS_MASK | SCG_CCR_DIVBUS_MASK)
|
|
|
|
/* A7 Plat clck = A7 Core Clock / 2 = 250MHz / 1 = 250MHz */
|
|
#define SCG1_RCCR_DIVBUS_NUM ((0x1) << SCG_CCR_DIVBUS_SHIFT)
|
|
#define SCG1_RCCR_CFG_NUM (SCG1_RCCR_SCS_NUM | SCG1_RCCR_DIVBUS_NUM)
|
|
|
|
void scg_a7_rccr_init(void)
|
|
{
|
|
u32 rccr_reg_val = 0;
|
|
|
|
rccr_reg_val = readl(&scg1_regs->rccr);
|
|
|
|
rccr_reg_val &= (~SCG1_RCCR_CFG_MASK);
|
|
rccr_reg_val |= (SCG1_RCCR_CFG_NUM);
|
|
|
|
writel(rccr_reg_val, &scg1_regs->rccr);
|
|
}
|
|
|
|
/* POSTDIV2 = 1 */
|
|
#define SCG1_SPLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
|
|
/* POSTDIV1 = 1 */
|
|
#define SCG1_SPLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
|
|
|
|
/* MULT = 22 */
|
|
#define SCG1_SPLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
|
|
|
|
/* PFD0 output clock selected */
|
|
#define SCG1_SPLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
|
|
/* PREDIV = 1 */
|
|
#define SCG1_SPLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
|
|
/* SPLL output clocks (including PFD outputs) selected */
|
|
#define SCG1_SPLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
|
|
/* SPLL PFD output clock selected */
|
|
#define SCG1_SPLL_CFG_PLLSEL_NUM ((0x1) << SCG_PLL_CFG_PLLSEL_SHIFT)
|
|
/* Clock source is System OSC */
|
|
#define SCG1_SPLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
|
|
#define SCG1_SPLL_CFG_NUM_24M_OSC (SCG1_SPLL_CFG_POSTDIV2_NUM | \
|
|
SCG1_SPLL_CFG_POSTDIV1_NUM | \
|
|
(22 << SCG_PLL_CFG_MULT_SHIFT) | \
|
|
SCG1_SPLL_CFG_PFDSEL_NUM | \
|
|
SCG1_SPLL_CFG_PREDIV_NUM | \
|
|
SCG1_SPLL_CFG_BYPASS_NUM | \
|
|
SCG1_SPLL_CFG_PLLSEL_NUM | \
|
|
SCG1_SPLL_CFG_CLKSRC_NUM)
|
|
/*413Mhz = A7 SPLL(528MHz) * 18/23 */
|
|
#define SCG1_SPLL_PFD0_FRAC_NUM ((23) << SCG_PLL_PFD0_FRAC_SHIFT)
|
|
|
|
void scg_a7_spll_init(void)
|
|
{
|
|
u32 val = 0;
|
|
|
|
/* Disable A7 System PLL */
|
|
val = readl(&scg1_regs->spllcsr);
|
|
val &= ~SCG_SPLL_CSR_SPLLEN_MASK;
|
|
writel(val, &scg1_regs->spllcsr);
|
|
|
|
/*
|
|
* Per block guide,
|
|
* "When changing PFD values, it is recommneded PFDx clock
|
|
* gets gated first by writing a value of 1 to PFDx_CLKGATE register,
|
|
* then program the new PFD value, then poll the PFDx_VALID
|
|
* flag to set before writing a value of 0 to PFDx_CLKGATE
|
|
* to ungate the PFDx clock and allow PFDx clock to run"
|
|
*/
|
|
|
|
/* Gate off A7 SPLL PFD0 ~ PDF4 */
|
|
val = readl(&scg1_regs->spllpfd);
|
|
val |= (SCG_PLL_PFD3_GATE_MASK |
|
|
SCG_PLL_PFD2_GATE_MASK |
|
|
SCG_PLL_PFD1_GATE_MASK |
|
|
SCG_PLL_PFD0_GATE_MASK);
|
|
writel(val, &scg1_regs->spllpfd);
|
|
|
|
/* ================ A7 SPLL Configuration Start ============== */
|
|
|
|
/* Configure A7 System PLL */
|
|
writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg);
|
|
|
|
/* Enable A7 System PLL */
|
|
val = readl(&scg1_regs->spllcsr);
|
|
val |= SCG_SPLL_CSR_SPLLEN_MASK;
|
|
writel(val, &scg1_regs->spllcsr);
|
|
|
|
/* Wait for A7 SPLL clock ready */
|
|
while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK))
|
|
;
|
|
|
|
/* Configure A7 SPLL PFD0 */
|
|
val = readl(&scg1_regs->spllpfd);
|
|
val &= ~SCG_PLL_PFD0_FRAC_MASK;
|
|
val |= SCG1_SPLL_PFD0_FRAC_NUM;
|
|
writel(val, &scg1_regs->spllpfd);
|
|
|
|
/* Un-gate A7 SPLL PFD0 */
|
|
val = readl(&scg1_regs->spllpfd);
|
|
val &= ~SCG_PLL_PFD0_GATE_MASK;
|
|
writel(val, &scg1_regs->spllpfd);
|
|
|
|
/* Wait for A7 SPLL PFD0 clock being valid */
|
|
while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK))
|
|
;
|
|
|
|
/* ================ A7 SPLL Configuration End ============== */
|
|
}
|
|
|
|
/* DDR clock source is APLL PFD0 (396MHz) */
|
|
#define SCG1_DDRCCR_DDRCS_NUM ((0x0) << SCG_DDRCCR_DDRCS_SHIFT)
|
|
/* DDR clock = APLL PFD0 / 1 = 396MHz / 1 = 396MHz */
|
|
#define SCG1_DDRCCR_DDRDIV_NUM ((0x1) << SCG_DDRCCR_DDRDIV_SHIFT)
|
|
/* DDR clock = APLL PFD0 / 2 = 396MHz / 2 = 198MHz */
|
|
#define SCG1_DDRCCR_DDRDIV_LF_NUM ((0x2) << SCG_DDRCCR_DDRDIV_SHIFT)
|
|
#define SCG1_DDRCCR_CFG_NUM (SCG1_DDRCCR_DDRCS_NUM | \
|
|
SCG1_DDRCCR_DDRDIV_NUM)
|
|
#define SCG1_DDRCCR_CFG_LF_NUM (SCG1_DDRCCR_DDRCS_NUM | \
|
|
SCG1_DDRCCR_DDRDIV_LF_NUM)
|
|
void scg_a7_ddrclk_init(void)
|
|
{
|
|
writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr);
|
|
}
|
|
|
|
/* SCG1(A7) APLLCFG configurations */
|
|
/* divide by 1 <<28 */
|
|
#define SCG1_APLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
|
|
/* divide by 1 <<24 */
|
|
#define SCG1_APLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
|
|
/* MULT is 22 <<16 */
|
|
#define SCG1_APLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
|
|
/* PFD0 output clock selected <<14 */
|
|
#define SCG1_APLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
|
|
/* PREDIV = 1 <<8 */
|
|
#define SCG1_APLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
|
|
/* APLL output clocks (including PFD outputs) selected <<2 */
|
|
#define SCG1_APLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
|
|
/* APLL PFD output clock selected <<1 */
|
|
#define SCG1_APLL_CFG_PLLSEL_NUM ((0x0) << SCG_PLL_CFG_PLLSEL_SHIFT)
|
|
/* Clock source is System OSC <<0 */
|
|
#define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
|
|
|
|
/*
|
|
* A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz,
|
|
* system PLL is sourced from APLL,
|
|
* APLL clock source is system OSC (24MHz)
|
|
*/
|
|
#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \
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SCG1_APLL_CFG_POSTDIV1_NUM | \
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(22 << SCG_PLL_CFG_MULT_SHIFT) | \
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SCG1_APLL_CFG_PFDSEL_NUM | \
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SCG1_APLL_CFG_PREDIV_NUM | \
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SCG1_APLL_CFG_BYPASS_NUM | \
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SCG1_APLL_CFG_PLLSEL_NUM | \
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SCG1_APLL_CFG_CLKSRC_NUM)
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/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */
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#define SCG1_APLL_PFD0_FRAC_NUM (27)
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void scg_a7_apll_init(void)
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{
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u32 val = 0;
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/* Disable A7 Auxiliary PLL */
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val = readl(&scg1_regs->apllcsr);
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val &= ~SCG_APLL_CSR_APLLEN_MASK;
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writel(val, &scg1_regs->apllcsr);
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/* Gate off A7 APLL PFD0 ~ PDF4 */
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val = readl(&scg1_regs->apllpfd);
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val |= 0x80808080;
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writel(val, &scg1_regs->apllpfd);
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/* ================ A7 APLL Configuration Start ============== */
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/* Configure A7 Auxiliary PLL */
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writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);
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/* Enable A7 Auxiliary PLL */
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val = readl(&scg1_regs->apllcsr);
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val |= SCG_APLL_CSR_APLLEN_MASK;
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writel(val, &scg1_regs->apllcsr);
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/* Wait for A7 APLL clock ready */
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while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))
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;
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/* Configure A7 APLL PFD0 */
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val = readl(&scg1_regs->apllpfd);
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val &= ~SCG_PLL_PFD0_FRAC_MASK;
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val |= SCG1_APLL_PFD0_FRAC_NUM;
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writel(val, &scg1_regs->apllpfd);
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/* Un-gate A7 APLL PFD0 */
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val = readl(&scg1_regs->apllpfd);
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val &= ~SCG_PLL_PFD0_GATE_MASK;
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writel(val, &scg1_regs->apllpfd);
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/* Wait for A7 APLL PFD0 clock being valid */
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while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))
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;
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}
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/* SCG1(A7) FIRC DIV configurations */
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/* Disable FIRC DIV3 */
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#define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)
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/* FIRC DIV2 = 48MHz / 1 = 48MHz */
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#define SCG1_FIRCDIV_DIV2_NUM ((0x1) << SCG_FIRCDIV_DIV2_SHIFT)
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/* Disable FIRC DIV1 */
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#define SCG1_FIRCDIV_DIV1_NUM ((0x0) << SCG_FIRCDIV_DIV1_SHIFT)
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void scg_a7_firc_init(void)
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{
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/* Wait for FIRC clock ready */
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while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK))
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;
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/* Configure A7 FIRC DIV1 ~ DIV3 */
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writel((SCG1_FIRCDIV_DIV3_NUM |
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SCG1_FIRCDIV_DIV2_NUM |
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SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv);
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}
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/* SCG1(A7) NICCCR configurations */
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/* NIC clock source is DDR clock (396/198MHz) */
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#define SCG1_NICCCR_NICCS_NUM ((0x1) << SCG_NICCCR_NICCS_SHIFT)
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/* NIC0 clock = DDR Clock / 2 = 396MHz / 2 = 198MHz */
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#define SCG1_NICCCR_NIC0_DIV_NUM ((0x1) << SCG_NICCCR_NIC0_DIV_SHIFT)
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/* NIC0 clock = DDR Clock / 1 = 198MHz / 1 = 198MHz */
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#define SCG1_NICCCR_NIC0_DIV_LF_NUM ((0x0) << SCG_NICCCR_NIC0_DIV_SHIFT)
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/* NIC1 clock = NIC0 Clock / 1 = 198MHz / 2 = 198MHz */
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#define SCG1_NICCCR_NIC1_DIV_NUM ((0x0) << SCG_NICCCR_NIC1_DIV_SHIFT)
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/* NIC1 bus clock = NIC1 Clock / 3 = 198MHz / 3 = 66MHz */
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#define SCG1_NICCCR_NIC1_DIVBUS_NUM ((0x2) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
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#define SCG1_NICCCR_CFG_NUM (SCG1_NICCCR_NICCS_NUM | \
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SCG1_NICCCR_NIC0_DIV_NUM | \
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SCG1_NICCCR_NIC1_DIV_NUM | \
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SCG1_NICCCR_NIC1_DIVBUS_NUM)
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void scg_a7_nicclk_init(void)
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{
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writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr);
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}
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/* SCG1(A7) FIRC DIV configurations */
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/* Enable FIRC DIV3 */
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#define SCG1_SOSCDIV_DIV3_NUM ((0x1) << SCG_SOSCDIV_DIV3_SHIFT)
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/* FIRC DIV2 = 48MHz / 1 = 48MHz */
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#define SCG1_SOSCDIV_DIV2_NUM ((0x1) << SCG_SOSCDIV_DIV2_SHIFT)
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/* Enable FIRC DIV1 */
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#define SCG1_SOSCDIV_DIV1_NUM ((0x1) << SCG_SOSCDIV_DIV1_SHIFT)
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void scg_a7_soscdiv_init(void)
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{
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/* Wait for FIRC clock ready */
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while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK))
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;
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/* Configure A7 FIRC DIV1 ~ DIV3 */
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writel((SCG1_SOSCDIV_DIV3_NUM | SCG1_SOSCDIV_DIV2_NUM |
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SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv);
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}
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void scg_a7_sys_clk_sel(enum scg_sys_src clk)
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{
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u32 rccr_reg_val = 0;
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clk_debug("%s: system clock selected as %s\n", "[SCG]",
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clk == SCG_SCS_SYS_OSC ? "SYS_OSC" :
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clk == SCG_SCS_SLOW_IRC ? "SLOW_IRC" :
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clk == SCG_SCS_FAST_IRC ? "FAST_IRC" :
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clk == SCG_SCS_RTC_OSC ? "RTC_OSC" :
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clk == SCG_SCS_AUX_PLL ? "AUX_PLL" :
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clk == SCG_SCS_SYS_PLL ? "SYS_PLL" :
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clk == SCG_SCS_USBPHY_PLL ? "USBPHY_PLL" :
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"Invalid source"
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);
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rccr_reg_val = readl(&scg1_regs->rccr);
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rccr_reg_val &= ~SCG_CCR_SCS_MASK;
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rccr_reg_val |= (clk << SCG_CCR_SCS_SHIFT);
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writel(rccr_reg_val, &scg1_regs->rccr);
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}
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void scg_a7_info(void)
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{
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debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid));
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debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param));
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debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));
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debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));
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}
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