mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-04 15:27:19 +00:00
8daa786211
There is difference between licenses in the Linux kernel and there shouldn't be any diff because all changes are coming from the same source at the same time. The difference is really in a time when they were upstreamed. That's why sync it up. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/813b29378083153b67c60772f28cd2613519f338.1695378830.git.michal.simek@amd.com
883 lines
18 KiB
Text
883 lines
18 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP ZCU111
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*
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* (C) Copyright 2017 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "ZynqMP ZCU111 RevA";
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compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci1;
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nvmem0 = &eeprom;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &dcc;
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spi0 = &qspi;
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usb0 = &usb0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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/* Another 4GB connected to PL */
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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switch-19 {
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label = "sw19";
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gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_DOWN>;
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wakeup-source;
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autorepeat;
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};
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};
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leds {
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compatible = "gpio-leds";
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heartbeat-led {
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label = "heartbeat";
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gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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ina226-u67 {
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compatible = "iio-hwmon";
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io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
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};
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ina226-u59 {
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compatible = "iio-hwmon";
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io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
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};
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ina226-u61 {
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compatible = "iio-hwmon";
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io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
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};
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ina226-u60 {
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compatible = "iio-hwmon";
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io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
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};
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ina226-u64 {
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compatible = "iio-hwmon";
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io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
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};
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ina226-u69 {
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compatible = "iio-hwmon";
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io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
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};
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ina226-u66 {
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compatible = "iio-hwmon";
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io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
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};
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ina226-u65 {
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compatible = "iio-hwmon";
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io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
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};
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ina226-u63 {
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compatible = "iio-hwmon";
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io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
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};
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ina226-u3 {
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compatible = "iio-hwmon";
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io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
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};
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ina226-u71 {
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compatible = "iio-hwmon";
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io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
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};
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ina226-u77 {
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compatible = "iio-hwmon";
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io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
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};
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ina226-u73 {
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compatible = "iio-hwmon";
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io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
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};
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ina226-u79 {
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compatible = "iio-hwmon";
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io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
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};
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/* 48MHz reference crystal */
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ref48: ref48M {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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};
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&dcc {
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status = "okay";
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};
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&fpd_dma_chan1 {
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status = "okay";
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};
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&fpd_dma_chan2 {
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status = "okay";
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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};
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&gem3 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@c {
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#phy-cells = <1>;
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compatible = "ethernet-phy-id2000.a231";
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&gpio {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_default>;
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};
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&gpu {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c0_default>;
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pinctrl-1 = <&pinctrl_i2c0_gpio>;
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scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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tca6416_u22: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller; /* interrupt not connected */
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#gpio-cells = <2>;
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/*
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* IRQ not connected
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* Lines:
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* 0 - MAX6643_OT_B
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* 1 - MAX6643_FANFAIL_B
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* 2 - MIO26_PMU_INPUT_LS
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* 4 - SFP_SI5382_INT_ALM
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* 5 - IIC_MUX_RESET_B
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* 6 - GEM3_EXP_RESET_B
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* 10 - FMCP_HSPC_PRSNT_M2C_B
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* 11 - CLK_SPI_MUX_SEL0
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* 12 - CLK_SPI_MUX_SEL1
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* 16 - IRPS5401_ALERT_B
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* 17 - INA226_PMBUS_ALERT
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* 3, 7, 13-15 - not connected
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*/
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};
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i2c-mux@75 { /* u23 */
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compatible = "nxp,pca9544";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x75>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* PS_PMBUS */
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/* PMBUS_ALERT done via pca9544 */
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u67: ina226@40 { /* u67 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u67";
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reg = <0x40>;
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shunt-resistor = <2000>;
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};
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u59: ina226@41 { /* u59 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u59";
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reg = <0x41>;
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shunt-resistor = <5000>;
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};
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u61: ina226@42 { /* u61 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u61";
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reg = <0x42>;
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shunt-resistor = <5000>;
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};
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u60: ina226@43 { /* u60 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u60";
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reg = <0x43>;
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shunt-resistor = <5000>;
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};
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u64: ina226@45 { /* u64 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u64";
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reg = <0x45>;
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shunt-resistor = <5000>;
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};
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u69: ina226@46 { /* u69 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u69";
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reg = <0x46>;
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shunt-resistor = <2000>;
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};
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u66: ina226@47 { /* u66 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u66";
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reg = <0x47>;
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shunt-resistor = <5000>;
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};
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u65: ina226@48 { /* u65 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u65";
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reg = <0x48>;
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shunt-resistor = <5000>;
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};
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u63: ina226@49 { /* u63 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u63";
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reg = <0x49>;
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shunt-resistor = <5000>;
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};
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u3: ina226@4a { /* u3 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u3";
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reg = <0x4a>;
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shunt-resistor = <5000>;
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};
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u71: ina226@4b { /* u71 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u71";
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reg = <0x4b>;
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shunt-resistor = <5000>;
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};
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u77: ina226@4c { /* u77 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u77";
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reg = <0x4c>;
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shunt-resistor = <5000>;
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};
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u73: ina226@4d { /* u73 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u73";
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reg = <0x4d>;
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shunt-resistor = <5000>;
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};
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u79: ina226@4e { /* u79 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u79";
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reg = <0x4e>;
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shunt-resistor = <5000>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* NC */
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
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compatible = "infineon,irps5401";
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reg = <0x43>;
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};
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irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
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compatible = "infineon,irps5401";
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reg = <0x44>;
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};
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irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
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compatible = "infineon,irps5401";
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reg = <0x45>;
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};
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/* u68 IR38064 +0 */
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/* u70 IR38060 +1 */
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/* u74 IR38060 +2 */
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/* u75 IR38060 +6 */
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/* J19 header too */
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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/* SYSMON */
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};
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};
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-mux@74 { /* u26 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/*
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* IIC_EEPROM 1kB memory which uses 256B blocks
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* where every block has different address.
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* 0 - 256B address 0x54
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* 256B - 512B address 0x55
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* 512B - 768B address 0x56
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* 768B - 1024B address 0x57
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*/
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eeprom: eeprom@54 { /* u88 */
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compatible = "atmel,24c08";
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reg = <0x54>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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si5341: clock-generator@36 { /* SI5341 - u46 */
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compatible = "silabs,si5341";
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reg = <0x36>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&ref48>;
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clock-names = "xtal";
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clock-output-names = "si5341";
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si5341_0: out@0 {
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/* refclk0 for PS-GT, used for DP */
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reg = <0>;
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always-on;
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};
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si5341_2: out@2 {
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/* refclk2 for PS-GT, used for USB3 */
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reg = <2>;
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always-on;
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};
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si5341_3: out@3 {
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/* refclk3 for PS-GT, used for SATA */
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reg = <3>;
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always-on;
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};
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si5341_5: out@5 {
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/* refclk5 PL CLK100 */
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reg = <5>;
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always-on;
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};
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si5341_6: out@6 {
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/* refclk6 PL CLK125 */
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reg = <6>;
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always-on;
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};
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si5341_9: out@9 {
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/* refclk9 used for PS_REF_CLK 33.3 MHz */
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reg = <9>;
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always-on;
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};
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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si570_1: clock-generator@5d { /* USER SI570 - u47 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>;
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temperature-stability = <50>;
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factory-fout = <300000000>;
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clock-frequency = <300000000>;
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clock-output-names = "si570_user";
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>;
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temperature-stability = <50>;
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factory-fout = <156250000>;
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clock-frequency = <156250000>;
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clock-output-names = "si570_mgt";
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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/* SI5382 - u48 */
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};
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i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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sc18is603@2f { /* sc18is602 - u93 */
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compatible = "nxp,sc18is603";
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reg = <0x2f>;
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/* 4 gpios for CS not handled by driver */
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/*
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* USB2ANY cable or
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* LMK04208 - u90 or
|
|
* LMX2594 - u102 or
|
|
* LMX2594 - u103 or
|
|
* LMX2594 - u104
|
|
*/
|
|
};
|
|
};
|
|
i2c@6 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <6>;
|
|
/* FMC connector */
|
|
};
|
|
/* 7 NC */
|
|
};
|
|
|
|
i2c-mux@75 {
|
|
compatible = "nxp,pca9548"; /* u27 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x75>;
|
|
|
|
i2c@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
/* FMCP_HSPC_IIC */
|
|
};
|
|
i2c@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
/* NC */
|
|
};
|
|
i2c@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
/* SYSMON */
|
|
};
|
|
i2c@3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <3>;
|
|
/* DDR4 SODIMM */
|
|
};
|
|
i2c@4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
/* SFP3 */
|
|
};
|
|
i2c@5 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <5>;
|
|
/* SFP2 */
|
|
};
|
|
i2c@6 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <6>;
|
|
/* SFP1 */
|
|
};
|
|
i2c@7 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <7>;
|
|
/* SFP0 */
|
|
};
|
|
};
|
|
};
|
|
|
|
&pinctrl0 {
|
|
status = "okay";
|
|
pinctrl_i2c0_default: i2c0-default {
|
|
mux {
|
|
groups = "i2c0_3_grp";
|
|
function = "i2c0";
|
|
};
|
|
|
|
conf {
|
|
groups = "i2c0_3_grp";
|
|
bias-pull-up;
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
};
|
|
};
|
|
|
|
pinctrl_i2c0_gpio: i2c0-gpio {
|
|
mux {
|
|
groups = "gpio0_14_grp", "gpio0_15_grp";
|
|
function = "gpio0";
|
|
};
|
|
|
|
conf {
|
|
groups = "gpio0_14_grp", "gpio0_15_grp";
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
};
|
|
};
|
|
|
|
pinctrl_i2c1_default: i2c1-default {
|
|
mux {
|
|
groups = "i2c1_4_grp";
|
|
function = "i2c1";
|
|
};
|
|
|
|
conf {
|
|
groups = "i2c1_4_grp";
|
|
bias-pull-up;
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
};
|
|
};
|
|
|
|
pinctrl_i2c1_gpio: i2c1-gpio {
|
|
mux {
|
|
groups = "gpio0_16_grp", "gpio0_17_grp";
|
|
function = "gpio0";
|
|
};
|
|
|
|
conf {
|
|
groups = "gpio0_16_grp", "gpio0_17_grp";
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
};
|
|
};
|
|
|
|
pinctrl_uart0_default: uart0-default {
|
|
mux {
|
|
groups = "uart0_4_grp";
|
|
function = "uart0";
|
|
};
|
|
|
|
conf {
|
|
groups = "uart0_4_grp";
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
};
|
|
|
|
conf-rx {
|
|
pins = "MIO18";
|
|
bias-high-impedance;
|
|
};
|
|
|
|
conf-tx {
|
|
pins = "MIO19";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pinctrl_usb0_default: usb0-default {
|
|
mux {
|
|
groups = "usb0_0_grp";
|
|
function = "usb0";
|
|
};
|
|
|
|
conf {
|
|
groups = "usb0_0_grp";
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
};
|
|
|
|
conf-rx {
|
|
pins = "MIO52", "MIO53", "MIO55";
|
|
bias-high-impedance;
|
|
drive-strength = <12>;
|
|
slew-rate = <SLEW_RATE_FAST>;
|
|
};
|
|
|
|
conf-tx {
|
|
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
|
"MIO60", "MIO61", "MIO62", "MIO63";
|
|
bias-disable;
|
|
drive-strength = <4>;
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
};
|
|
};
|
|
|
|
pinctrl_gem3_default: gem3-default {
|
|
mux {
|
|
function = "ethernet3";
|
|
groups = "ethernet3_0_grp";
|
|
};
|
|
|
|
conf {
|
|
groups = "ethernet3_0_grp";
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
};
|
|
|
|
conf-rx {
|
|
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
|
"MIO75";
|
|
bias-high-impedance;
|
|
low-power-disable;
|
|
};
|
|
|
|
conf-tx {
|
|
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
|
"MIO69";
|
|
bias-disable;
|
|
low-power-enable;
|
|
};
|
|
|
|
mux-mdio {
|
|
function = "mdio3";
|
|
groups = "mdio3_0_grp";
|
|
};
|
|
|
|
conf-mdio {
|
|
groups = "mdio3_0_grp";
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pinctrl_sdhci1_default: sdhci1-default {
|
|
mux {
|
|
groups = "sdio1_0_grp";
|
|
function = "sdio1";
|
|
};
|
|
|
|
conf {
|
|
groups = "sdio1_0_grp";
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
bias-disable;
|
|
};
|
|
|
|
mux-cd {
|
|
groups = "sdio1_cd_0_grp";
|
|
function = "sdio1_cd";
|
|
};
|
|
|
|
conf-cd {
|
|
groups = "sdio1_cd_0_grp";
|
|
bias-high-impedance;
|
|
bias-pull-up;
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
};
|
|
};
|
|
|
|
pinctrl_gpio_default: gpio-default {
|
|
mux {
|
|
function = "gpio0";
|
|
groups = "gpio0_22_grp", "gpio0_23_grp";
|
|
};
|
|
|
|
conf {
|
|
groups = "gpio0_22_grp", "gpio0_23_grp";
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
};
|
|
|
|
mux-msp {
|
|
function = "gpio0";
|
|
groups = "gpio0_13_grp", "gpio0_38_grp";
|
|
};
|
|
|
|
conf-msp {
|
|
groups = "gpio0_13_grp", "gpio0_38_grp";
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
};
|
|
|
|
conf-pull-up {
|
|
pins = "MIO22";
|
|
bias-pull-up;
|
|
};
|
|
|
|
conf-pull-none {
|
|
pins = "MIO13", "MIO23", "MIO38";
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
&psgtr {
|
|
status = "okay";
|
|
/* nc, dp, usb3, sata */
|
|
clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
|
|
clock-names = "ref1", "ref2", "ref3";
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
is-dual = <1>;
|
|
flash@0 {
|
|
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x0>;
|
|
spi-tx-bus-width = <4>;
|
|
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
|
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
|
partition@0 { /* for testing purpose */
|
|
label = "qspi-fsbl-uboot";
|
|
reg = <0x0 0x100000>;
|
|
};
|
|
partition@100000 { /* for testing purpose */
|
|
label = "qspi-linux";
|
|
reg = <0x100000 0x500000>;
|
|
};
|
|
partition@600000 { /* for testing purpose */
|
|
label = "qspi-device-tree";
|
|
reg = <0x600000 0x20000>;
|
|
};
|
|
partition@620000 { /* for testing purpose */
|
|
label = "qspi-rootfs";
|
|
reg = <0x620000 0x5E0000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&rtc {
|
|
status = "okay";
|
|
};
|
|
|
|
&sata {
|
|
status = "okay";
|
|
/* SATA OOB timing settings */
|
|
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
|
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
|
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
|
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
|
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
|
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
|
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
|
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
|
phy-names = "sata-phy";
|
|
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
|
|
};
|
|
|
|
/* SD1 with level shifter */
|
|
&sdhci1 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
|
disable-wp;
|
|
/*
|
|
* This property should be removed for supporting UHS mode
|
|
*/
|
|
no-1-8-v;
|
|
xlnx,mio-bank = <1>;
|
|
};
|
|
|
|
&uart0 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart0_default>;
|
|
};
|
|
|
|
/* ULPI SMSC USB3320 */
|
|
&usb0 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb0_default>;
|
|
phy-names = "usb3-phy";
|
|
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
|
};
|
|
|
|
&dwc3_0 {
|
|
status = "okay";
|
|
dr_mode = "host";
|
|
snps,usb3_lpm_capable;
|
|
maximum-speed = "super-speed";
|
|
};
|
|
|
|
&zynqmp_dpdma {
|
|
status = "okay";
|
|
};
|
|
|
|
&zynqmp_dpsub {
|
|
status = "okay";
|
|
phy-names = "dp-phy0", "dp-phy1";
|
|
phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
|
|
<&psgtr 0 PHY_TYPE_DP 1 1>;
|
|
};
|