mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 14:23:00 +00:00
f0c0b3a9e6
A large number of boards incorrectly used getenv() in their board init code running before relocation. In some cases this caused U-Boot to hang when certain environment variables grew too long. Fix the code to use getenv_r(). Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: The LEOX team <team@leox.org> Cc: Michael Schwingen <michael@schwingen.org> Cc: Georg Schardt <schardt@team-ctech.de> Cc: Werner Pfister <Pfister_Werner@intercontrol.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Peter De Schrijver <p2@mind.be> Cc: John Zhan <zhanz@sinovee.com> Cc: Rishi Bhattacharya <rishi@ti.com> Cc: Peter Tyser <ptyser@xes-inc.com>
177 lines
4 KiB
C
177 lines
4 KiB
C
/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#include <miiphy.h>
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#include <gdsys_fpga.h>
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#define PHYREG_CONTROL 0
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#define PHYREG_PAGE_ADDRESS 22
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#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
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#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
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enum {
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UNITTYPE_CCD_SWITCH = 1,
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};
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enum {
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HWVER_100 = 0,
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HWVER_110 = 1,
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HWVER_121 = 2,
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HWVER_122 = 3,
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};
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int configure_gbit_phy(unsigned char addr)
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{
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unsigned short value;
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/* select page 2 */
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if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_PAGE_ADDRESS, 0x0002))
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goto err_out;
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/* disable SGMII autonegotiation */
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if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
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goto err_out;
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/* select page 0 */
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if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_PAGE_ADDRESS, 0x0000))
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goto err_out;
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/* switch from powerdown to normal operation */
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if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
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goto err_out;
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if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
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goto err_out;
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/* reset phy so settings take effect */
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if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_CONTROL, 0x9140))
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goto err_out;
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return 0;
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err_out:
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printf("Error writing to the PHY addr=%02x\n", addr);
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return -1;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
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u16 versions = in_le16(&fpga->versions);
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u16 fpga_version = in_le16(&fpga->fpga_version);
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u16 fpga_features = in_le16(&fpga->fpga_features);
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unsigned unit_type;
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unsigned hardware_version;
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unsigned feature_channels;
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unsigned feature_expansion;
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unit_type = (versions & 0xf000) >> 12;
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hardware_version = versions & 0x000f;
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feature_channels = fpga_features & 0x007f;
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feature_expansion = fpga_features & (1<<15);
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printf("Board: ");
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printf("CATCenter Io");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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puts("\n ");
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switch (unit_type) {
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case UNITTYPE_CCD_SWITCH:
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printf("CCD-Switch");
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break;
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default:
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printf("UnitType %d(not supported)", unit_type);
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break;
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}
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switch (hardware_version) {
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case HWVER_100:
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printf(" HW-Ver 1.00\n");
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break;
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case HWVER_110:
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printf(" HW-Ver 1.10\n");
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break;
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case HWVER_121:
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printf(" HW-Ver 1.21\n");
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break;
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case HWVER_122:
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printf(" HW-Ver 1.22\n");
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break;
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default:
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printf(" HW-Ver %d(not supported)\n",
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hardware_version);
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break;
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}
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printf(" FPGA V %d.%02d, features:",
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fpga_version / 100, fpga_version % 100);
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printf(" %d channel(s)", feature_channels);
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printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
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return 0;
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}
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/*
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* setup Gbit PHYs
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*/
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int last_stage_init(void)
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{
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
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unsigned int k;
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miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
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bb_miiphy_read, bb_miiphy_write);
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for (k = 0; k < 32; ++k)
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configure_gbit_phy(k);
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/* take fpga serdes blocks out of reset */
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out_le16(&fpga->quad_serdes_reset, 0);
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return 0;
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}
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