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https://github.com/AsahiLinux/u-boot
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8d4c759f2c
If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF data pins interferes with the BootROM's boot mode sampling. So shut the controller down. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
310 lines
7.1 KiB
C
310 lines
7.1 KiB
C
/*
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* Freescale i.MX28 common code
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* 1 second delay should be plenty of time for block reset. */
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#define RESET_MAX_TIMEOUT 1000000
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#define MX28_BLOCK_SFTRST (1 << 31)
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#define MX28_BLOCK_CLKGATE (1 << 30)
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/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
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inline void lowlevel_init(void) {}
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void reset_cpu(ulong ignored) __attribute__((noreturn));
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void reset_cpu(ulong ignored)
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{
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struct mx28_rtc_regs *rtc_regs =
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(struct mx28_rtc_regs *)MXS_RTC_BASE;
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struct mx28_lcdif_regs *lcdif_regs =
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(struct mx28_lcdif_regs *)MXS_LCDIF_BASE;
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/*
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* Shut down the LCD controller as it interferes with BootROM boot mode
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* pads sampling.
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*/
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writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
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/* Wait 1 uS before doing the actual watchdog reset */
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writel(1, &rtc_regs->hw_rtc_watchdog);
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writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
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/* Endless loop, reset will exit from here */
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for (;;)
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;
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}
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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icache_enable();
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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dcache_enable();
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#endif
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}
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int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
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{
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while (--timeout) {
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if ((readl(®->reg) & mask) == mask)
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break;
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udelay(1);
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}
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return !timeout;
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}
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int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
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{
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while (--timeout) {
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if ((readl(®->reg) & mask) == 0)
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break;
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udelay(1);
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}
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return !timeout;
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}
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int mx28_reset_block(struct mx28_register_32 *reg)
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{
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/* Clear SFTRST */
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writel(MX28_BLOCK_SFTRST, ®->reg_clr);
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if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear CLKGATE */
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writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
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/* Set SFTRST */
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writel(MX28_BLOCK_SFTRST, ®->reg_set);
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/* Wait for CLKGATE being set */
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if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear SFTRST */
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writel(MX28_BLOCK_SFTRST, ®->reg_clr);
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if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear CLKGATE */
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writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
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if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
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return 1;
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return 0;
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}
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void mx28_fixup_vt(uint32_t start_addr)
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{
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uint32_t *vt = (uint32_t *)0x20;
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int i;
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for (i = 0; i < 8; i++)
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vt[i] = start_addr + (4 * i);
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}
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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mx28_fixup_vt(gd->relocaddr);
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return 0;
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}
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#endif
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#ifdef CONFIG_ARCH_CPU_INIT
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int arch_cpu_init(void)
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{
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struct mx28_clkctrl_regs *clkctrl_regs =
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(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
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extern uint32_t _start;
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mx28_fixup_vt((uint32_t)&_start);
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/*
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* Enable NAND clock
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*/
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/* Clear bypass bit */
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writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
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&clkctrl_regs->hw_clkctrl_clkseq_set);
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/* Set GPMI clock to ref_gpmi / 12 */
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clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
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CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
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udelay(1000);
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/*
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* Configure GPIO unit
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*/
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mxs_gpio_init();
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#ifdef CONFIG_APBH_DMA
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/* Start APBH DMA */
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mxs_dma_init();
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#endif
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return 0;
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}
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#endif
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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struct mx28_spl_data *data = (struct mx28_spl_data *)
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((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
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printf("Freescale i.MX28 family at %d MHz\n",
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode);
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return 0;
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}
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#endif
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int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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{
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printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
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printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
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printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
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printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
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return 0;
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}
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/*
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* Initializes on-chip ethernet controllers.
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*/
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#ifdef CONFIG_CMD_NET
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int cpu_eth_init(bd_t *bis)
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{
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struct mx28_clkctrl_regs *clkctrl_regs =
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(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
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/* Turn on ENET clocks */
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clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
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CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
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/* Set up ENET PLL for 50 MHz */
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/* Power on ENET PLL */
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writel(CLKCTRL_PLL2CTRL0_POWER,
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&clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
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udelay(10);
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/* Gate on ENET PLL */
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writel(CLKCTRL_PLL2CTRL0_CLKGATE,
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&clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
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/* Enable pad output */
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setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
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return 0;
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}
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#endif
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static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
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{
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mac[0] = 0x00;
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mac[1] = 0x04; /* Use FSL vendor MAC address by default */
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if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
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mac[5] += 1;
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}
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void mx28_adjust_mac(int dev_id, unsigned char *mac)
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__attribute__((weak, alias("__mx28_adjust_mac")));
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#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
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#define MXS_OCOTP_MAX_TIMEOUT 1000000
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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struct mx28_ocotp_regs *ocotp_regs =
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(struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
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uint32_t data;
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memset(mac, 0, 6);
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writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
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if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
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MXS_OCOTP_MAX_TIMEOUT)) {
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printf("MXS FEC: Can't get MAC from OCOTP\n");
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return;
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}
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data = readl(&ocotp_regs->hw_ocotp_cust0);
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mac[2] = (data >> 24) & 0xff;
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mac[3] = (data >> 16) & 0xff;
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mac[4] = (data >> 8) & 0xff;
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mac[5] = data & 0xff;
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mx28_adjust_mac(dev_id, mac);
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}
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#else
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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memset(mac, 0, 6);
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}
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#endif
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int mx28_dram_init(void)
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{
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struct mx28_spl_data *data = (struct mx28_spl_data *)
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((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
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if (data->mem_dram_size == 0) {
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printf("MX28:\n"
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"Error, the RAM size passed up from SPL is 0!\n");
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hang();
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}
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gd->ram_size = data->mem_dram_size;
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return 0;
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}
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U_BOOT_CMD(
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clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
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"display clocks",
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""
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);
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