Jagan Teki aefc0b7a60 clk: sunxi: h3: Implement EPHY CLK and RESET ... EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respective clock and reset reg and bits. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>		2019-03-09 13:16:35 +05:30
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clk_a10.c	clk: sunxi: Implement A10 EMAC clocks	2019-03-09 13:16:35 +05:30
clk_a10s.c	clk: sunxi: Implement A10 EMAC clocks	2019-03-09 13:16:35 +05:30
clk_a23.c	clk: sunxi: Implement SPI clocks, resets	2019-03-04 18:08:56 +05:30
clk_a31.c	clk: sunxi: Implement EMAC, GMAC clocks, resets	2019-03-09 13:16:35 +05:30
clk_a64.c	clk: sunxi: Implement EMAC, GMAC clocks, resets	2019-03-09 13:16:35 +05:30
clk_a80.c	clk: sunxi: Implement SPI clocks, resets	2019-03-04 18:08:56 +05:30
clk_a83t.c	clk: sunxi: Implement EMAC, GMAC clocks, resets	2019-03-09 13:16:35 +05:30
clk_h3.c	clk: sunxi: h3: Implement EPHY CLK and RESET	2019-03-09 13:16:35 +05:30
clk_h6.c	clk: sunxi: Implement EMAC, GMAC clocks, resets	2019-03-09 13:16:35 +05:30
clk_r40.c	clk: sunxi: Implement EMAC, GMAC clocks, resets	2019-03-09 13:16:35 +05:30
clk_sunxi.c	sunxi: clk: enable clk and reset for CCU devices	2019-01-30 18:21:35 +05:30
clk_v3s.c	clk: sunxi: Implement SPI clocks, resets	2019-03-04 18:08:56 +05:30
Kconfig	clk: sunxi: Add Allwinner A80 CLK driver	2019-01-18 22:19:09 +05:30
Makefile	clk: sunxi: Add Allwinner A80 CLK driver	2019-01-18 22:19:09 +05:30