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https://github.com/AsahiLinux/u-boot
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89a54abf1b
To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
539 lines
15 KiB
C
539 lines
15 KiB
C
/*
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* Copyright Altera Corporation (C) 2014-2015
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <div64.h>
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#include <watchdog.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/system_manager.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct sdram_prot_rule {
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u32 sdram_start; /* SDRAM start address */
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u32 sdram_end; /* SDRAM end address */
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u32 rule; /* SDRAM protection rule number: 0-19 */
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int valid; /* Rule valid or not? 1 - valid, 0 not*/
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u32 security;
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u32 portmask;
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u32 result;
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u32 lo_prot_id;
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u32 hi_prot_id;
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};
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static struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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static struct socfpga_sdr_ctrl *sdr_ctrl =
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(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
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/**
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* get_errata_rows() - Up the number of DRAM rows to cover entire address space
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* @cfg: SDRAM controller configuration data
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*
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* SDRAM Failure happens when accessing non-existent memory. Artificially
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* increase the number of rows so that the memory controller thinks it has
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* 4GB of RAM. This function returns such amount of rows.
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*/
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static int get_errata_rows(const struct socfpga_sdram_config *cfg)
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{
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/* Define constant for 4G memory - used for SDRAM errata workaround */
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#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
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const unsigned long long memsize = MEMSIZE_4G;
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const unsigned int cs =
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((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
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SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
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const unsigned int rows =
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(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
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SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
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const unsigned int banks =
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(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
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SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
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const unsigned int cols =
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(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
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SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
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const unsigned int width = 8;
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unsigned long long newrows;
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int bits, inewrowslog2;
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debug("workaround rows - memsize %lld\n", memsize);
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debug("workaround rows - cs %d\n", cs);
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debug("workaround rows - width %d\n", width);
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debug("workaround rows - rows %d\n", rows);
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debug("workaround rows - banks %d\n", banks);
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debug("workaround rows - cols %d\n", cols);
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newrows = lldiv(memsize, cs * (width / 8));
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debug("rows workaround - term1 %lld\n", newrows);
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newrows = lldiv(newrows, (1 << banks) * (1 << cols));
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debug("rows workaround - term2 %lld\n", newrows);
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/*
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* Compute the hamming weight - same as number of bits set.
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* Need to see if result is ordinal power of 2 before
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* attempting log2 of result.
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*/
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bits = generic_hweight32(newrows);
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debug("rows workaround - bits %d\n", bits);
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if (bits != 1) {
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printf("SDRAM workaround failed, bits set %d\n", bits);
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return rows;
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}
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if (newrows > UINT_MAX) {
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printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
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return rows;
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}
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inewrowslog2 = __ilog2(newrows);
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debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
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if (inewrowslog2 == -1) {
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printf("SDRAM workaround failed, newrows %lld\n", newrows);
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return rows;
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}
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return inewrowslog2;
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}
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/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
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static void sdram_set_rule(struct sdram_prot_rule *prule)
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{
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u32 lo_addr_bits;
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u32 hi_addr_bits;
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int ruleno = prule->rule;
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/* Select the rule */
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writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
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/* Obtain the address bits */
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lo_addr_bits = prule->sdram_start >> 20ULL;
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hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
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debug("sdram set rule start %x, %d\n", lo_addr_bits,
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prule->sdram_start);
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debug("sdram set rule end %x, %d\n", hi_addr_bits,
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prule->sdram_end);
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/* Set rule addresses */
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writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
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/* Set rule protection ids */
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writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
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&sdr_ctrl->prot_rule_id);
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/* Set the rule data */
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writel(prule->security | (prule->valid << 2) |
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(prule->portmask << 3) | (prule->result << 13),
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&sdr_ctrl->prot_rule_data);
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/* write the rule */
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writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
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/* Set rule number to 0 by default */
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writel(0, &sdr_ctrl->prot_rule_rdwr);
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}
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static void sdram_get_rule(struct sdram_prot_rule *prule)
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{
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u32 addr;
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u32 id;
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u32 data;
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int ruleno = prule->rule;
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/* Read the rule */
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writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
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writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
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/* Get the addresses */
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addr = readl(&sdr_ctrl->prot_rule_addr);
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prule->sdram_start = (addr & 0xFFF) << 20;
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prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
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/* Get the configured protection IDs */
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id = readl(&sdr_ctrl->prot_rule_id);
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prule->lo_prot_id = id & 0xFFF;
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prule->hi_prot_id = (id >> 12) & 0xFFF;
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/* Get protection data */
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data = readl(&sdr_ctrl->prot_rule_data);
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prule->security = data & 0x3;
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prule->valid = (data >> 2) & 0x1;
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prule->portmask = (data >> 3) & 0x3FF;
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prule->result = (data >> 13) & 0x1;
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}
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static void
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sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
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{
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struct sdram_prot_rule rule;
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int rules;
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/* Start with accepting all SDRAM transaction */
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writel(0x0, &sdr_ctrl->protport_default);
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/* Clear all protection rules for warm boot case */
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memset(&rule, 0, sizeof(rule));
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for (rules = 0; rules < 20; rules++) {
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rule.rule = rules;
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sdram_set_rule(&rule);
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}
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/* new rule: accept SDRAM */
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rule.sdram_start = sdram_start;
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rule.sdram_end = sdram_end;
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rule.lo_prot_id = 0x0;
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rule.hi_prot_id = 0xFFF;
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rule.portmask = 0x3FF;
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rule.security = 0x3;
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rule.result = 0;
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rule.valid = 1;
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rule.rule = 0;
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/* set new rule */
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sdram_set_rule(&rule);
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/* default rule: reject everything */
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writel(0x3ff, &sdr_ctrl->protport_default);
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}
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static void sdram_dump_protection_config(void)
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{
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struct sdram_prot_rule rule;
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int rules;
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debug("SDRAM Prot rule, default %x\n",
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readl(&sdr_ctrl->protport_default));
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for (rules = 0; rules < 20; rules++) {
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rule.rule = rules;
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sdram_get_rule(&rule);
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debug("Rule %d, rules ...\n", rules);
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debug(" sdram start %x\n", rule.sdram_start);
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debug(" sdram end %x\n", rule.sdram_end);
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debug(" low prot id %d, hi prot id %d\n",
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rule.lo_prot_id,
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rule.hi_prot_id);
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debug(" portmask %x\n", rule.portmask);
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debug(" security %d\n", rule.security);
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debug(" result %d\n", rule.result);
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debug(" valid %d\n", rule.valid);
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}
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}
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/**
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* sdram_write_verify() - write to register and verify the write.
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* @addr: Register address
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* @val: Value to be written and verified
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*
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* This function writes to a register, reads back the value and compares
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* the result with the written value to check if the data match.
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*/
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static unsigned sdram_write_verify(const u32 *addr, const u32 val)
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{
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u32 rval;
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debug(" Write - Address 0x%p Data 0x%08x\n", addr, val);
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writel(val, addr);
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debug(" Read and verify...");
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rval = readl(addr);
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if (rval != val) {
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debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
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addr, val, rval);
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return -EINVAL;
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}
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debug("correct!\n");
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return 0;
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}
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/**
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* sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
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* @cfg: SDRAM controller configuration data
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*
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* Return the value of DRAM CTRLCFG register.
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*/
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static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
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{
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const u32 csbits =
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((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
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SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
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u32 addrorder =
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(cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
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SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
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u32 ctrl_cfg = cfg->ctrl_cfg;
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/*
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* SDRAM Failure When Accessing Non-Existent Memory
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* Set the addrorder field of the SDRAM control register
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* based on the CSBITs setting.
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*/
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if (csbits == 1) {
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if (addrorder != 0)
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debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
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addrorder = 0;
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} else if (csbits == 2) {
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if (addrorder != 2)
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debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
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addrorder = 2;
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}
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ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
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ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
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return ctrl_cfg;
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}
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/**
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* sdr_get_addr_rw() - Get the value of DRAM ADDRW register
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* @cfg: SDRAM controller configuration data
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*
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* Return the value of DRAM ADDRW register.
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*/
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static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
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{
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/*
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* SDRAM Failure When Accessing Non-Existent Memory
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* Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
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* log2(number of chip select bits). Since there's only
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* 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
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* which is the same as "chip selects" - 1.
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*/
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const int rows = get_errata_rows(cfg);
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u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
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return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
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}
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/**
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* sdr_load_regs() - Load SDRAM controller registers
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* @cfg: SDRAM controller configuration data
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*
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* This function loads the register values into the SDRAM controller block.
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*/
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static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
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{
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const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
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const u32 dram_addrw = sdr_get_addr_rw(cfg);
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debug("\nConfiguring CTRLCFG\n");
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writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
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debug("Configuring DRAMTIMING1\n");
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writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
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debug("Configuring DRAMTIMING2\n");
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writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
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debug("Configuring DRAMTIMING3\n");
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writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
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debug("Configuring DRAMTIMING4\n");
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writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
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debug("Configuring LOWPWRTIMING\n");
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writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
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debug("Configuring DRAMADDRW\n");
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writel(dram_addrw, &sdr_ctrl->dram_addrw);
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debug("Configuring DRAMIFWIDTH\n");
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writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
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debug("Configuring DRAMDEVWIDTH\n");
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writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
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debug("Configuring LOWPWREQ\n");
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writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
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debug("Configuring DRAMINTR\n");
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writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
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debug("Configuring STATICCFG\n");
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writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
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debug("Configuring CTRLWIDTH\n");
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writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
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debug("Configuring PORTCFG\n");
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writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
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debug("Configuring FIFOCFG\n");
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writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
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debug("Configuring MPPRIORITY\n");
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writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
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debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
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writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
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writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
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writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
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writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
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debug("Configuring MPPACING_MPPACING_0\n");
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writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
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writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
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writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
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writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
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debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
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writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
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writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
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writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
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debug("Configuring PHYCTRL_PHYCTRL_0\n");
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writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
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debug("Configuring CPORTWIDTH\n");
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writel(cfg->cport_width, &sdr_ctrl->cport_width);
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debug("Configuring CPORTWMAP\n");
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writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
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debug("Configuring CPORTRMAP\n");
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writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
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debug("Configuring RFIFOCMAP\n");
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writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
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debug("Configuring WFIFOCMAP\n");
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writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
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debug("Configuring CPORTRDWR\n");
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writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
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debug("Configuring DRAMODT\n");
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writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
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debug("Configuring EXTRATIME1\n");
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writel(cfg->extratime1, &sdr_ctrl->extratime1);
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}
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/**
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* sdram_mmr_init_full() - Function to initialize SDRAM MMR
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* @sdr_phy_reg: Value of the PHY control register 0
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*
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* Initialize the SDRAM MMR.
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*/
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int sdram_mmr_init_full(unsigned int sdr_phy_reg)
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{
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const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
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const unsigned int rows =
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(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
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SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
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int ret;
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writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
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sdr_load_regs(cfg);
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/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
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writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
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/* only enable if the FPGA is programmed */
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if (fpgamgr_test_fpga_ready()) {
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ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
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cfg->fpgaport_rst);
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if (ret)
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return ret;
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}
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/* Restore the SDR PHY Register if valid */
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if (sdr_phy_reg != 0xffffffff)
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writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
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/* Final step - apply configuration changes */
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debug("Configuring STATICCFG\n");
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clrsetbits_le32(&sdr_ctrl->static_cfg,
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SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
|
|
1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
|
|
|
|
sdram_set_protection_config(0, sdram_calculate_size() - 1);
|
|
|
|
sdram_dump_protection_config();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* sdram_calculate_size() - Calculate SDRAM size
|
|
*
|
|
* Calculate SDRAM device size based on SDRAM controller parameters.
|
|
* Size is specified in bytes.
|
|
*/
|
|
unsigned long sdram_calculate_size(void)
|
|
{
|
|
unsigned long temp;
|
|
unsigned long row, bank, col, cs, width;
|
|
const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
|
|
const unsigned int csbits =
|
|
((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
|
|
SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
|
|
const unsigned int rowbits =
|
|
(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
|
|
SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
|
|
|
|
temp = readl(&sdr_ctrl->dram_addrw);
|
|
col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
|
|
SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
|
|
|
|
/*
|
|
* SDRAM Failure When Accessing Non-Existent Memory
|
|
* Use ROWBITS from Quartus/QSys to calculate SDRAM size
|
|
* since the FB specifies we modify ROWBITs to work around SDRAM
|
|
* controller issue.
|
|
*/
|
|
row = readl(&sysmgr_regs->iswgrp_handoff[4]);
|
|
if (row == 0)
|
|
row = rowbits;
|
|
/*
|
|
* If the stored handoff value for rows is greater than
|
|
* the field width in the sdr.dramaddrw register then
|
|
* something is very wrong. Revert to using the the #define
|
|
* value handed off by the SOCEDS tool chain instead of
|
|
* using a broken value.
|
|
*/
|
|
if (row > 31)
|
|
row = rowbits;
|
|
|
|
bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
|
|
SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
|
|
|
|
/*
|
|
* SDRAM Failure When Accessing Non-Existent Memory
|
|
* Use CSBITs from Quartus/QSys to calculate SDRAM size
|
|
* since the FB specifies we modify CSBITs to work around SDRAM
|
|
* controller issue.
|
|
*/
|
|
cs = csbits;
|
|
|
|
width = readl(&sdr_ctrl->dram_if_width);
|
|
|
|
/* ECC would not be calculated as its not addressible */
|
|
if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
|
|
width = 32;
|
|
if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
|
|
width = 16;
|
|
|
|
/* calculate the SDRAM size base on this info */
|
|
temp = 1 << (row + bank + col);
|
|
temp = temp * cs * (width / 8);
|
|
|
|
debug("%s returns %ld\n", __func__, temp);
|
|
|
|
return temp;
|
|
}
|