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8cc92b996d
The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding new ones. Having flags would be better than adding new members every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
110 lines
2.7 KiB
C
110 lines
2.7 KiB
C
/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __PINCTRL_UNIPHIER_H__
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#define __PINCTRL_UNIPHIER_H__
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#define UNIPHIER_PINCTRL_PINMUX_BASE 0x0
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#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700
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#define UNIPHIER_PINCTRL_IECTRL 0xd00
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#define UNIPHIER_PIN_ATTR_PACKED(iectrl) (iectrl)
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static inline unsigned int uniphier_pin_get_iectrl(unsigned long data)
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{
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return data;
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}
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/**
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* struct uniphier_pinctrl_pin - pin data for UniPhier SoC
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*
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* @number: pin number
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* @data: additional per-pin data
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*/
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struct uniphier_pinctrl_pin {
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unsigned number;
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unsigned long data;
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};
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/**
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* struct uniphier_pinctrl_group - pin group data for UniPhier SoC
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*
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* @name: pin group name
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* @pins: array of pins that belong to the group
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* @num_pins: number of pins in the group
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* @muxvals: array of values to be set to pinmux registers
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*/
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struct uniphier_pinctrl_group {
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const char *name;
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const unsigned *pins;
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unsigned num_pins;
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const unsigned *muxvals;
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};
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/**
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* struct uniphier_pinctrl_socdata - SoC data for UniPhier pin controller
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*
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* @pins: array of pin data
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* @pins_count: number of pin data
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* @groups: array of pin group data
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* @groups_count: number of pin group data
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* @functions: array of pinmux function names
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* @functions_count: number of pinmux functions
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* @mux_bits: bit width of each pinmux register
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* @reg_stride: stride of pinmux register address
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* @caps: SoC-specific capability flag
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*/
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struct uniphier_pinctrl_socdata {
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const struct uniphier_pinctrl_pin *pins;
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int pins_count;
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const struct uniphier_pinctrl_group *groups;
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int groups_count;
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const char * const *functions;
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int functions_count;
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unsigned caps;
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#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
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};
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#define UNIPHIER_PINCTRL_PIN(a, b) \
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{ \
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.number = a, \
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.data = UNIPHIER_PIN_ATTR_PACKED(b), \
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}
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#define UNIPHIER_PINCTRL_GROUP(grp) \
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{ \
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.name = #grp, \
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.pins = grp##_pins, \
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.num_pins = ARRAY_SIZE(grp##_pins), \
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.muxvals = grp##_muxvals + \
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BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
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ARRAY_SIZE(grp##_muxvals)), \
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}
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/**
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* struct uniphier_pinctrl_priv - private data for UniPhier pinctrl driver
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*
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* @base: base address of the pinctrl device
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* @socdata: SoC specific data
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*/
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struct uniphier_pinctrl_priv {
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void __iomem *base;
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struct uniphier_pinctrl_socdata *socdata;
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};
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extern const struct pinctrl_ops uniphier_pinctrl_ops;
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int uniphier_pinctrl_probe(struct udevice *dev,
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struct uniphier_pinctrl_socdata *socdata);
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int uniphier_pinctrl_remove(struct udevice *dev);
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#endif /* __PINCTRL_UNIPHIER_H__ */
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