mirror of
https://github.com/AsahiLinux/u-boot
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6cc04547cb
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
205 lines
5.4 KiB
C
205 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef _FSL_ICID_H_
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#define _FSL_ICID_H_
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#include <asm/types.h>
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#include <fsl_qbman.h>
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#include <fsl_sec.h>
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#include <asm/armv8/sec_firmware.h>
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struct icid_id_table {
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#ifndef CONFIG_SPL_BUILD
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const char *compat;
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phys_addr_t compat_addr;
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#endif
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phys_addr_t reg_addr;
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u32 reg;
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#ifndef CONFIG_SPL_BUILD
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u32 id;
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#endif
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bool le;
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};
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struct fman_icid_id_table {
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u32 port_id;
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u32 icid;
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};
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u32 get_ppid_icid(int ppid_tbl_idx, int ppid);
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int fdt_get_smmu_phandle(void *blob);
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int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
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void set_icids(void);
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void fdt_fixup_icid(void *blob);
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#ifdef CONFIG_SPL_BUILD
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#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
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{ .reg = regA, \
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.reg_addr = addr, \
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.le = _le \
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}
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#else
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#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
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{ .compat = name, \
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.id = idA, \
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.reg = regA, \
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.compat_addr = compataddr, \
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.reg_addr = addr, \
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.le = _le \
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}
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#endif
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#ifdef CONFIG_SYS_FSL_SEC_LE
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#define SEC_IS_LE true
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#elif defined(CONFIG_SYS_FSL_SEC_BE)
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#define SEC_IS_LE false
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#endif
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#ifdef CONFIG_FSL_LSCH2
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#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define SCFG_IS_LE true
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#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
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#define SCFG_IS_LE false
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#endif
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#define QDMA_IS_LE false
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#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
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SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
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offsetof(struct ccsr_scfg, name) + CFG_SYS_FSL_SCFG_ADDR, \
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compataddr, SCFG_IS_LE)
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#define SET_USB_ICID(usb_num, compat, streamid) \
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SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
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CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
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#define SET_SATA_ICID(compat, streamid) \
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SET_SCFG_ICID(compat, streamid, sata_icid,\
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AHCI_BASE_ADDR)
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#define SET_SDHC_ICID(streamid) \
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SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
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CFG_SYS_FSL_ESDHC_ADDR)
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#define SET_EDMA_ICID(streamid) \
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SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
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EDMA_BASE_ADDR)
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#define SET_ETR_ICID(streamid) \
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SET_SCFG_ICID(NULL, streamid, etr_icid, 0)
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#define SET_DEBUG_ICID(streamid) \
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SET_SCFG_ICID(NULL, streamid, debug_icid, 0)
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#define SET_QE_ICID(streamid) \
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SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\
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QE_BASE_ADDR)
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#define SET_QMAN_ICID(streamid) \
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SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
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offsetof(struct ccsr_qman, liodnr) + \
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CFG_SYS_FSL_QMAN_ADDR, \
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CFG_SYS_FSL_QMAN_ADDR, false)
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#define SET_BMAN_ICID(streamid) \
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SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
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offsetof(struct ccsr_bman, liodnr) + \
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CFG_SYS_FSL_BMAN_ADDR, \
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CFG_SYS_FSL_BMAN_ADDR, false)
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#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
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{ .port_id = (_port_id), .icid = (streamid) }
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#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
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#define SET_SEC_QI_ICID(streamid) \
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SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
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0, offsetof(ccsr_sec_t, qilcr_ls) + \
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CFG_SYS_FSL_SEC_ADDR, \
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CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
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extern struct fman_icid_id_table fman_icid_tbl[];
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extern int fman_icid_tbl_sz;
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#else /* CONFIG_FSL_LSCH2 */
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#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
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#define GUR_IS_LE true
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#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
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#define GUR_IS_LE false
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#endif
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#define QDMA_IS_LE true
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#define SET_GUR_ICID(compat, streamid, name, compataddr) \
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SET_ICID_ENTRY(compat, streamid, streamid, \
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offsetof(struct ccsr_gur, name) + CFG_SYS_FSL_GUTS_ADDR, \
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compataddr, GUR_IS_LE)
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#define SET_USB_ICID(usb_num, compat, streamid) \
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SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
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CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
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#define SET_SATA_ICID(sata_num, compat, streamid) \
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SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
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AHCI_BASE_ADDR##sata_num)
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#define SET_SDHC_ICID(sdhc_num, streamid) \
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SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\
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FSL_ESDHC##sdhc_num##_BASE_ADDR)
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#define SET_EDMA_ICID(streamid) \
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SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\
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EDMA_BASE_ADDR)
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#define SET_GPU_ICID(compat, streamid) \
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SET_GUR_ICID(compat, streamid, misc1_amqr,\
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GPU_BASE_ADDR)
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#define SET_DISPLAY_ICID(streamid) \
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SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\
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DISPLAY_BASE_ADDR)
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#define SEC_ICID_REG_VAL(streamid) (streamid)
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#endif /* CONFIG_FSL_LSCH2 */
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#define SET_QDMA_ICID(compat, streamid) \
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SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
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QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
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QDMA_BASE_ADDR, QDMA_IS_LE), \
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SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
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QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
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QDMA_BASE_ADDR, QDMA_IS_LE)
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#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
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SET_ICID_ENTRY( \
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(CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
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(FSL_SEC_JR##jr_num##_OFFSET == \
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SEC_JR3_OFFSET + CFG_SYS_FSL_SEC_OFFSET) \
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? NULL \
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: "fsl,sec-v4.0-job-ring"), \
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streamid, \
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SEC_ICID_REG_VAL(streamid), \
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offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
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CFG_SYS_FSL_SEC_ADDR, \
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FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
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#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
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SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
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offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
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CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
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#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
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SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
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offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
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CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
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extern struct icid_id_table icid_tbl[];
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extern int icid_tbl_sz;
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#endif
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