mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 01:17:39 +00:00
49a3e0b9e2
Initially investigating a Linux network issue causing a lot of drop and
poor network performances on a custom system based on a TQMA6A module
(based on an iMX6Q), [1st link below].
I eventually correlated my observations with a contention at the NIC
level when in concurrency with the graphics pipeline. Troubleshooting
this in the kernel lead to disabling DMA bursts accesses made by the IPU
in order to avoid triggering the QoS at the interconnect level, reducing
from 50 to 10% the drop rate on eth0, [2nd link below]. The solution
worked on my setup but not on others, which still suffered from
abnormally high drop rates even with this "fix".
After looking a while into TQ Systems BSP I figured out a number of
differences in recent U-Boot out-of-tree patches they had in their
repository [3rd link]. Parsing the differences one after the other lead
me to this final solution.
The reset pad of the DDR controller was apparently misconfigured, Bit
18-19 picturing the "DDR select field". The current value b11 is
reserved. The only defined value as of version 6 of the iMX6Q manual was
b00 "DDR3 and LPDDR2 mode". In practice no register difference has been
spotted after changing this configuration but all issues tracked thus
far just vanished. All previous fixes have been proven irrelevant. Just
clearing this field solved all our network issues and the drop rate as
measured by iperf3 felt back to 0%.
Link: https://lore.kernel.org/netdev/20231012193410.3d1812cf@xps-13/
Link: https://lists.freedesktop.org/archives/dri-devel/2023-October/428251.html
Link: 15eb6abbef
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
123 lines
4.1 KiB
INI
123 lines
4.1 KiB
INI
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
|
|
*
|
|
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
|
|
* and create imximage boot image
|
|
*
|
|
* The syntax is taken as close as possible with the kwbimage
|
|
*/
|
|
|
|
/* image version */
|
|
IMAGE_VERSION 2
|
|
|
|
#include <config.h>
|
|
|
|
/*
|
|
* Boot Device : one of
|
|
* spi, sd (the board has no nand neither onenand)
|
|
*/
|
|
#if defined(CONFIG_TQMA6X_MMC_BOOT)
|
|
BOOT_FROM sd
|
|
#elif defined(CONFIG_TQMA6X_SPI_BOOT)
|
|
BOOT_FROM spi
|
|
#endif
|
|
|
|
#include "asm/arch/mx6-ddr.h"
|
|
#include "asm/arch/iomux.h"
|
|
#include "asm/arch/crm_regs.h"
|
|
|
|
/* TQMa6Q/D DDR config Rev. 0100B */
|
|
/* IOMUX configuration */
|
|
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
|
|
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030
|
|
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
|
|
DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
|
|
DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
|
|
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_RESET, 0x00003030
|
|
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
|
|
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
|
|
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
|
|
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
|
|
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
|
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
|
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
|
|
|
|
/* memory interface calibration values */
|
|
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
|
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B
|
|
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016
|
|
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C
|
|
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348
|
|
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304
|
|
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436
|
|
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242
|
|
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440
|
|
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
|
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
|
|
|
/* configure memory interface */
|
|
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
|
|
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
|
|
DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4
|
|
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
|
|
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
|
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
|
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
|
DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
|
|
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
|
|
DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
|
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
|
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
|
|
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
|
|
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536
|
|
DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
|
|
|
#include "clocks.cfg"
|