mirror of
https://github.com/AsahiLinux/u-boot
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a0f5a61dc1
Add reset ID defines for rk3588.
commit <0a8eb7dae617> ("dt-bindings: reset: add rk3588 reset
definitions")
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
754 lines
20 KiB
C
754 lines
20 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
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* Copyright (c) 2022 Collabora Ltd.
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*
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* Author: Elaine Zhang <zhangqing@rock-chips.com>
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* Author: Sebastian Reichel <sebastian.reichel@collabora.com>
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*/
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#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
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#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
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#define SRST_A_TOP_BIU 0
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#define SRST_P_TOP_BIU 1
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#define SRST_P_CSIPHY0 2
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#define SRST_CSIPHY0 3
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#define SRST_P_CSIPHY1 4
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#define SRST_CSIPHY1 5
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#define SRST_A_TOP_M500_BIU 6
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#define SRST_A_TOP_M400_BIU 7
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#define SRST_A_TOP_S200_BIU 8
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#define SRST_A_TOP_S400_BIU 9
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#define SRST_A_TOP_M300_BIU 10
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#define SRST_USBDP_COMBO_PHY0_INIT 11
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#define SRST_USBDP_COMBO_PHY0_CMN 12
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#define SRST_USBDP_COMBO_PHY0_LANE 13
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#define SRST_USBDP_COMBO_PHY0_PCS 14
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#define SRST_USBDP_COMBO_PHY1_INIT 15
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#define SRST_USBDP_COMBO_PHY1_CMN 16
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#define SRST_USBDP_COMBO_PHY1_LANE 17
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#define SRST_USBDP_COMBO_PHY1_PCS 18
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#define SRST_DCPHY0 19
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#define SRST_P_MIPI_DCPHY0 20
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#define SRST_P_MIPI_DCPHY0_GRF 21
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#define SRST_DCPHY1 22
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#define SRST_P_MIPI_DCPHY1 23
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#define SRST_P_MIPI_DCPHY1_GRF 24
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#define SRST_P_APB2ASB_SLV_CDPHY 25
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#define SRST_P_APB2ASB_SLV_CSIPHY 26
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#define SRST_P_APB2ASB_SLV_VCCIO3_5 27
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#define SRST_P_APB2ASB_SLV_VCCIO6 28
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#define SRST_P_APB2ASB_SLV_EMMCIO 29
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#define SRST_P_APB2ASB_SLV_IOC_TOP 30
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#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31
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#define SRST_P_CRU 32
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#define SRST_A_CHANNEL_SECURE2VO1USB 33
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#define SRST_A_CHANNEL_SECURE2CENTER 34
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#define SRST_H_CHANNEL_SECURE2VO1USB 35
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#define SRST_H_CHANNEL_SECURE2CENTER 36
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#define SRST_P_CHANNEL_SECURE2VO1USB 37
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#define SRST_P_CHANNEL_SECURE2CENTER 38
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#define SRST_H_AUDIO_BIU 39
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#define SRST_P_AUDIO_BIU 40
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#define SRST_H_I2S0_8CH 41
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#define SRST_M_I2S0_8CH_TX 42
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#define SRST_M_I2S0_8CH_RX 43
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#define SRST_P_ACDCDIG 44
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#define SRST_H_I2S2_2CH 45
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#define SRST_H_I2S3_2CH 46
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#define SRST_M_I2S2_2CH 47
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#define SRST_M_I2S3_2CH 48
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#define SRST_DAC_ACDCDIG 49
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#define SRST_H_SPDIF0 50
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#define SRST_M_SPDIF0 51
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#define SRST_H_SPDIF1 52
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#define SRST_M_SPDIF1 53
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#define SRST_H_PDM1 54
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#define SRST_PDM1 55
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#define SRST_A_BUS_BIU 56
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#define SRST_P_BUS_BIU 57
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#define SRST_A_GIC 58
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#define SRST_A_GIC_DBG 59
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#define SRST_A_DMAC0 60
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#define SRST_A_DMAC1 61
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#define SRST_A_DMAC2 62
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#define SRST_P_I2C1 63
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#define SRST_P_I2C2 64
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#define SRST_P_I2C3 65
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#define SRST_P_I2C4 66
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#define SRST_P_I2C5 67
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#define SRST_P_I2C6 68
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#define SRST_P_I2C7 69
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#define SRST_P_I2C8 70
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#define SRST_I2C1 71
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#define SRST_I2C2 72
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#define SRST_I2C3 73
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#define SRST_I2C4 74
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#define SRST_I2C5 75
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#define SRST_I2C6 76
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#define SRST_I2C7 77
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#define SRST_I2C8 78
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#define SRST_P_CAN0 79
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#define SRST_CAN0 80
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#define SRST_P_CAN1 81
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#define SRST_CAN1 82
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#define SRST_P_CAN2 83
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#define SRST_CAN2 84
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#define SRST_P_SARADC 85
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#define SRST_P_TSADC 86
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#define SRST_TSADC 87
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#define SRST_P_UART1 88
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#define SRST_P_UART2 89
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#define SRST_P_UART3 90
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#define SRST_P_UART4 91
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#define SRST_P_UART5 92
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#define SRST_P_UART6 93
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#define SRST_P_UART7 94
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#define SRST_P_UART8 95
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#define SRST_P_UART9 96
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#define SRST_S_UART1 97
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#define SRST_S_UART2 98
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#define SRST_S_UART3 99
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#define SRST_S_UART4 100
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#define SRST_S_UART5 101
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#define SRST_S_UART6 102
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#define SRST_S_UART7 103
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#define SRST_S_UART8 104
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#define SRST_S_UART9 105
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#define SRST_P_SPI0 106
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#define SRST_P_SPI1 107
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#define SRST_P_SPI2 108
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#define SRST_P_SPI3 109
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#define SRST_P_SPI4 110
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#define SRST_SPI0 111
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#define SRST_SPI1 112
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#define SRST_SPI2 113
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#define SRST_SPI3 114
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#define SRST_SPI4 115
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#define SRST_P_WDT0 116
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#define SRST_T_WDT0 117
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#define SRST_P_SYS_GRF 118
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#define SRST_P_PWM1 119
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#define SRST_PWM1 120
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#define SRST_P_PWM2 121
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#define SRST_PWM2 122
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#define SRST_P_PWM3 123
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#define SRST_PWM3 124
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#define SRST_P_BUSTIMER0 125
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#define SRST_P_BUSTIMER1 126
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#define SRST_BUSTIMER0 127
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#define SRST_BUSTIMER1 128
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#define SRST_BUSTIMER2 129
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#define SRST_BUSTIMER3 130
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#define SRST_BUSTIMER4 131
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#define SRST_BUSTIMER5 132
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#define SRST_BUSTIMER6 133
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#define SRST_BUSTIMER7 134
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#define SRST_BUSTIMER8 135
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#define SRST_BUSTIMER9 136
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#define SRST_BUSTIMER10 137
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#define SRST_BUSTIMER11 138
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#define SRST_P_MAILBOX0 139
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#define SRST_P_MAILBOX1 140
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#define SRST_P_MAILBOX2 141
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#define SRST_P_GPIO1 142
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#define SRST_GPIO1 143
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#define SRST_P_GPIO2 144
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#define SRST_GPIO2 145
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#define SRST_P_GPIO3 146
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#define SRST_GPIO3 147
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#define SRST_P_GPIO4 148
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#define SRST_GPIO4 149
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#define SRST_A_DECOM 150
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#define SRST_P_DECOM 151
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#define SRST_D_DECOM 152
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#define SRST_P_TOP 153
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#define SRST_A_GICADB_GIC2CORE_BUS 154
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#define SRST_P_DFT2APB 155
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#define SRST_P_APB2ASB_MST_TOP 156
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#define SRST_P_APB2ASB_MST_CDPHY 157
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#define SRST_P_APB2ASB_MST_BOT_RIGHT 158
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#define SRST_P_APB2ASB_MST_IOC_TOP 159
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#define SRST_P_APB2ASB_MST_IOC_RIGHT 160
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#define SRST_P_APB2ASB_MST_CSIPHY 161
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#define SRST_P_APB2ASB_MST_VCCIO3_5 162
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#define SRST_P_APB2ASB_MST_VCCIO6 163
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#define SRST_P_APB2ASB_MST_EMMCIO 164
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#define SRST_A_SPINLOCK 165
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#define SRST_P_OTPC_NS 166
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#define SRST_OTPC_NS 167
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#define SRST_OTPC_ARB 168
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#define SRST_P_BUSIOC 169
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#define SRST_P_PMUCM0_INTMUX 170
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#define SRST_P_DDRCM0_INTMUX 171
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#define SRST_P_DDR_DFICTL_CH0 172
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#define SRST_P_DDR_MON_CH0 173
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#define SRST_P_DDR_STANDBY_CH0 174
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#define SRST_P_DDR_UPCTL_CH0 175
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#define SRST_TM_DDR_MON_CH0 176
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#define SRST_P_DDR_GRF_CH01 177
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#define SRST_DFI_CH0 178
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#define SRST_SBR_CH0 179
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#define SRST_DDR_UPCTL_CH0 180
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#define SRST_DDR_DFICTL_CH0 181
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#define SRST_DDR_MON_CH0 182
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#define SRST_DDR_STANDBY_CH0 183
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#define SRST_A_DDR_UPCTL_CH0 184
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#define SRST_P_DDR_DFICTL_CH1 185
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#define SRST_P_DDR_MON_CH1 186
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#define SRST_P_DDR_STANDBY_CH1 187
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#define SRST_P_DDR_UPCTL_CH1 188
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#define SRST_TM_DDR_MON_CH1 189
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#define SRST_DFI_CH1 190
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#define SRST_SBR_CH1 191
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#define SRST_DDR_UPCTL_CH1 192
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#define SRST_DDR_DFICTL_CH1 193
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#define SRST_DDR_MON_CH1 194
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#define SRST_DDR_STANDBY_CH1 195
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#define SRST_A_DDR_UPCTL_CH1 196
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#define SRST_A_DDR01_MSCH0 197
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#define SRST_A_DDR01_RS_MSCH0 198
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#define SRST_A_DDR01_FRS_MSCH0 199
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#define SRST_A_DDR01_SCRAMBLE0 200
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#define SRST_A_DDR01_FRS_SCRAMBLE0 201
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#define SRST_A_DDR01_MSCH1 202
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#define SRST_A_DDR01_RS_MSCH1 203
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#define SRST_A_DDR01_FRS_MSCH1 204
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#define SRST_A_DDR01_SCRAMBLE1 205
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#define SRST_A_DDR01_FRS_SCRAMBLE1 206
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#define SRST_P_DDR01_MSCH0 207
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#define SRST_P_DDR01_MSCH1 208
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#define SRST_P_DDR_DFICTL_CH2 209
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#define SRST_P_DDR_MON_CH2 210
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#define SRST_P_DDR_STANDBY_CH2 211
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#define SRST_P_DDR_UPCTL_CH2 212
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#define SRST_TM_DDR_MON_CH2 213
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#define SRST_P_DDR_GRF_CH23 214
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#define SRST_DFI_CH2 215
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#define SRST_SBR_CH2 216
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#define SRST_DDR_UPCTL_CH2 217
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#define SRST_DDR_DFICTL_CH2 218
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#define SRST_DDR_MON_CH2 219
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#define SRST_DDR_STANDBY_CH2 220
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#define SRST_A_DDR_UPCTL_CH2 221
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#define SRST_P_DDR_DFICTL_CH3 222
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#define SRST_P_DDR_MON_CH3 223
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#define SRST_P_DDR_STANDBY_CH3 224
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#define SRST_P_DDR_UPCTL_CH3 225
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#define SRST_TM_DDR_MON_CH3 226
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#define SRST_DFI_CH3 227
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#define SRST_SBR_CH3 228
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#define SRST_DDR_UPCTL_CH3 229
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#define SRST_DDR_DFICTL_CH3 230
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#define SRST_DDR_MON_CH3 231
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#define SRST_DDR_STANDBY_CH3 232
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#define SRST_A_DDR_UPCTL_CH3 233
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#define SRST_A_DDR23_MSCH2 234
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#define SRST_A_DDR23_RS_MSCH2 235
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#define SRST_A_DDR23_FRS_MSCH2 236
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#define SRST_A_DDR23_SCRAMBLE2 237
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#define SRST_A_DDR23_FRS_SCRAMBLE2 238
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#define SRST_A_DDR23_MSCH3 239
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#define SRST_A_DDR23_RS_MSCH3 240
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#define SRST_A_DDR23_FRS_MSCH3 241
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#define SRST_A_DDR23_SCRAMBLE3 242
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#define SRST_A_DDR23_FRS_SCRAMBLE3 243
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#define SRST_P_DDR23_MSCH2 244
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#define SRST_P_DDR23_MSCH3 245
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#define SRST_ISP1 246
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#define SRST_ISP1_VICAP 247
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#define SRST_A_ISP1_BIU 248
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#define SRST_H_ISP1_BIU 249
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#define SRST_A_RKNN1 250
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#define SRST_A_RKNN1_BIU 251
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#define SRST_H_RKNN1 252
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#define SRST_H_RKNN1_BIU 253
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#define SRST_A_RKNN2 254
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#define SRST_A_RKNN2_BIU 255
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#define SRST_H_RKNN2 256
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#define SRST_H_RKNN2_BIU 257
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#define SRST_A_RKNN_DSU0 258
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#define SRST_P_NPUTOP_BIU 259
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#define SRST_P_NPU_TIMER 260
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#define SRST_NPUTIMER0 261
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#define SRST_NPUTIMER1 262
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#define SRST_P_NPU_WDT 263
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#define SRST_T_NPU_WDT 264
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#define SRST_P_NPU_PVTM 265
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#define SRST_P_NPU_GRF 266
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#define SRST_NPU_PVTM 267
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#define SRST_NPU_PVTPLL 268
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#define SRST_H_NPU_CM0_BIU 269
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#define SRST_F_NPU_CM0_CORE 270
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#define SRST_T_NPU_CM0_JTAG 271
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#define SRST_A_RKNN0 272
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#define SRST_A_RKNN0_BIU 273
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#define SRST_H_RKNN0 274
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#define SRST_H_RKNN0_BIU 275
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#define SRST_H_NVM_BIU 276
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#define SRST_A_NVM_BIU 277
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#define SRST_H_EMMC 278
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#define SRST_A_EMMC 279
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#define SRST_C_EMMC 280
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#define SRST_B_EMMC 281
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#define SRST_T_EMMC 282
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#define SRST_S_SFC 283
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#define SRST_H_SFC 284
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#define SRST_H_SFC_XIP 285
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#define SRST_P_GRF 286
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#define SRST_P_DEC_BIU 287
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#define SRST_P_PHP_BIU 288
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#define SRST_A_PCIE_GRIDGE 289
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#define SRST_A_PHP_BIU 290
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#define SRST_A_GMAC0 291
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#define SRST_A_GMAC1 292
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#define SRST_A_PCIE_BIU 293
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#define SRST_PCIE0_POWER_UP 294
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#define SRST_PCIE1_POWER_UP 295
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#define SRST_PCIE2_POWER_UP 296
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#define SRST_PCIE3_POWER_UP 297
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#define SRST_PCIE4_POWER_UP 298
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#define SRST_P_PCIE0 299
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#define SRST_P_PCIE1 300
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#define SRST_P_PCIE2 301
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#define SRST_P_PCIE3 302
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#define SRST_P_PCIE4 303
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#define SRST_A_PHP_GIC_ITS 304
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#define SRST_A_MMU_PCIE 305
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#define SRST_A_MMU_PHP 306
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#define SRST_A_MMU_BIU 307
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#define SRST_A_USB3OTG2 308
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#define SRST_PMALIVE0 309
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#define SRST_PMALIVE1 310
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#define SRST_PMALIVE2 311
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#define SRST_A_SATA0 312
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#define SRST_A_SATA1 313
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#define SRST_A_SATA2 314
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#define SRST_RXOOB0 315
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#define SRST_RXOOB1 316
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#define SRST_RXOOB2 317
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#define SRST_ASIC0 318
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#define SRST_ASIC1 319
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#define SRST_ASIC2 320
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#define SRST_A_RKVDEC_CCU 321
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#define SRST_H_RKVDEC0 322
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#define SRST_A_RKVDEC0 323
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#define SRST_H_RKVDEC0_BIU 324
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#define SRST_A_RKVDEC0_BIU 325
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#define SRST_RKVDEC0_CA 326
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#define SRST_RKVDEC0_HEVC_CA 327
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#define SRST_RKVDEC0_CORE 328
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#define SRST_H_RKVDEC1 329
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#define SRST_A_RKVDEC1 330
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#define SRST_H_RKVDEC1_BIU 331
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#define SRST_A_RKVDEC1_BIU 332
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#define SRST_RKVDEC1_CA 333
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#define SRST_RKVDEC1_HEVC_CA 334
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#define SRST_RKVDEC1_CORE 335
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#define SRST_A_USB_BIU 336
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#define SRST_H_USB_BIU 337
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#define SRST_A_USB3OTG0 338
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#define SRST_A_USB3OTG1 339
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#define SRST_H_HOST0 340
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#define SRST_H_HOST_ARB0 341
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#define SRST_H_HOST1 342
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#define SRST_H_HOST_ARB1 343
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#define SRST_A_USB_GRF 344
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#define SRST_C_USB2P0_HOST0 345
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#define SRST_C_USB2P0_HOST1 346
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#define SRST_HOST_UTMI0 347
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#define SRST_HOST_UTMI1 348
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#define SRST_A_VDPU_BIU 349
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#define SRST_A_VDPU_LOW_BIU 350
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#define SRST_H_VDPU_BIU 351
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#define SRST_A_JPEG_DECODER_BIU 352
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#define SRST_A_VPU 353
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#define SRST_H_VPU 354
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#define SRST_A_JPEG_ENCODER0 355
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#define SRST_H_JPEG_ENCODER0 356
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#define SRST_A_JPEG_ENCODER1 357
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#define SRST_H_JPEG_ENCODER1 358
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#define SRST_A_JPEG_ENCODER2 359
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#define SRST_H_JPEG_ENCODER2 360
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#define SRST_A_JPEG_ENCODER3 361
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#define SRST_H_JPEG_ENCODER3 362
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#define SRST_A_JPEG_DECODER 363
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#define SRST_H_JPEG_DECODER 364
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#define SRST_H_IEP2P0 365
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#define SRST_A_IEP2P0 366
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#define SRST_IEP2P0_CORE 367
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#define SRST_H_RGA2 368
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#define SRST_A_RGA2 369
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#define SRST_RGA2_CORE 370
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#define SRST_H_RGA3_0 371
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#define SRST_A_RGA3_0 372
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#define SRST_RGA3_0_CORE 373
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#define SRST_H_RKVENC0_BIU 374
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#define SRST_A_RKVENC0_BIU 375
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#define SRST_H_RKVENC0 376
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#define SRST_A_RKVENC0 377
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#define SRST_RKVENC0_CORE 378
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#define SRST_H_RKVENC1_BIU 379
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#define SRST_A_RKVENC1_BIU 380
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#define SRST_H_RKVENC1 381
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#define SRST_A_RKVENC1 382
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#define SRST_RKVENC1_CORE 383
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#define SRST_A_VI_BIU 384
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#define SRST_H_VI_BIU 385
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#define SRST_P_VI_BIU 386
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#define SRST_D_VICAP 387
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#define SRST_A_VICAP 388
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#define SRST_H_VICAP 389
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#define SRST_ISP0 390
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#define SRST_ISP0_VICAP 391
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#define SRST_FISHEYE0 392
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#define SRST_FISHEYE1 393
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#define SRST_P_CSI_HOST_0 394
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#define SRST_P_CSI_HOST_1 395
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#define SRST_P_CSI_HOST_2 396
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#define SRST_P_CSI_HOST_3 397
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#define SRST_P_CSI_HOST_4 398
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#define SRST_P_CSI_HOST_5 399
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#define SRST_CSIHOST0_VICAP 400
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#define SRST_CSIHOST1_VICAP 401
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#define SRST_CSIHOST2_VICAP 402
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#define SRST_CSIHOST3_VICAP 403
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#define SRST_CSIHOST4_VICAP 404
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#define SRST_CSIHOST5_VICAP 405
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#define SRST_CIFIN 406
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#define SRST_A_VOP_BIU 407
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#define SRST_A_VOP_LOW_BIU 408
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#define SRST_H_VOP_BIU 409
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#define SRST_P_VOP_BIU 410
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#define SRST_H_VOP 411
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#define SRST_A_VOP 412
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#define SRST_D_VOP0 413
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#define SRST_D_VOP2HDMI_BRIDGE0 414
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#define SRST_D_VOP2HDMI_BRIDGE1 415
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#define SRST_D_VOP1 416
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#define SRST_D_VOP2 417
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#define SRST_D_VOP3 418
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#define SRST_P_VOPGRF 419
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#define SRST_P_DSIHOST0 420
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#define SRST_P_DSIHOST1 421
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#define SRST_DSIHOST0 422
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#define SRST_DSIHOST1 423
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#define SRST_VOP_PMU 424
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#define SRST_P_VOP_CHANNEL_BIU 425
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#define SRST_H_VO0_BIU 426
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#define SRST_H_VO0_S_BIU 427
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#define SRST_P_VO0_BIU 428
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#define SRST_P_VO0_S_BIU 429
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#define SRST_A_HDCP0_BIU 430
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#define SRST_P_VO0GRF 431
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#define SRST_H_HDCP_KEY0 432
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#define SRST_A_HDCP0 433
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#define SRST_H_HDCP0 434
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#define SRST_HDCP0 435
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#define SRST_P_TRNG0 436
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#define SRST_DP0 437
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#define SRST_DP1 438
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#define SRST_H_I2S4_8CH 439
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#define SRST_M_I2S4_8CH_TX 440
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#define SRST_H_I2S8_8CH 441
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#define SRST_M_I2S8_8CH_TX 442
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#define SRST_H_SPDIF2_DP0 443
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#define SRST_M_SPDIF2_DP0 444
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#define SRST_H_SPDIF5_DP1 445
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#define SRST_M_SPDIF5_DP1 446
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#define SRST_A_HDCP1_BIU 447
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#define SRST_A_VO1_BIU 448
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#define SRST_H_VOP1_BIU 449
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#define SRST_H_VOP1_S_BIU 450
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#define SRST_P_VOP1_BIU 451
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#define SRST_P_VO1GRF 452
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#define SRST_P_VO1_S_BIU 453
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#define SRST_H_I2S7_8CH 454
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#define SRST_M_I2S7_8CH_RX 455
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#define SRST_H_HDCP_KEY1 456
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#define SRST_A_HDCP1 457
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#define SRST_H_HDCP1 458
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#define SRST_HDCP1 459
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#define SRST_P_TRNG1 460
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#define SRST_P_HDMITX0 461
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#define SRST_HDMITX0_REF 462
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#define SRST_P_HDMITX1 463
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#define SRST_HDMITX1_REF 464
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#define SRST_A_HDMIRX 465
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#define SRST_P_HDMIRX 466
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#define SRST_HDMIRX_REF 467
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#define SRST_P_EDP0 468
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#define SRST_EDP0_24M 469
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#define SRST_P_EDP1 470
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#define SRST_EDP1_24M 471
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#define SRST_M_I2S5_8CH_TX 472
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#define SRST_H_I2S5_8CH 473
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#define SRST_M_I2S6_8CH_TX 474
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#define SRST_M_I2S6_8CH_RX 475
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#define SRST_H_I2S6_8CH 476
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#define SRST_H_SPDIF3 477
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#define SRST_M_SPDIF3 478
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#define SRST_H_SPDIF4 479
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#define SRST_M_SPDIF4 480
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#define SRST_H_SPDIFRX0 481
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#define SRST_M_SPDIFRX0 482
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#define SRST_H_SPDIFRX1 483
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#define SRST_M_SPDIFRX1 484
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#define SRST_H_SPDIFRX2 485
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|
#define SRST_M_SPDIFRX2 486
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#define SRST_LINKSYM_HDMITXPHY0 487
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#define SRST_LINKSYM_HDMITXPHY1 488
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#define SRST_VO1_BRIDGE0 489
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#define SRST_VO1_BRIDGE1 490
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#define SRST_H_I2S9_8CH 491
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#define SRST_M_I2S9_8CH_RX 492
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#define SRST_H_I2S10_8CH 493
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#define SRST_M_I2S10_8CH_RX 494
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#define SRST_P_S_HDMIRX 495
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|
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#define SRST_GPU 496
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#define SRST_SYS_GPU 497
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|
#define SRST_A_S_GPU_BIU 498
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#define SRST_A_M0_GPU_BIU 499
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#define SRST_A_M1_GPU_BIU 500
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#define SRST_A_M2_GPU_BIU 501
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#define SRST_A_M3_GPU_BIU 502
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#define SRST_P_GPU_BIU 503
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|
#define SRST_P_GPU_PVTM 504
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#define SRST_GPU_PVTM 505
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|
#define SRST_P_GPU_GRF 506
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|
#define SRST_GPU_PVTPLL 507
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#define SRST_GPU_JTAG 508
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|
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#define SRST_A_AV1_BIU 509
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#define SRST_A_AV1 510
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|
#define SRST_P_AV1_BIU 511
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|
#define SRST_P_AV1 512
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|
|
#define SRST_A_DDR_BIU 513
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|
#define SRST_A_DMA2DDR 514
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|
#define SRST_A_DDR_SHAREMEM 515
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|
#define SRST_A_DDR_SHAREMEM_BIU 516
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|
#define SRST_A_CENTER_S200_BIU 517
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|
#define SRST_A_CENTER_S400_BIU 518
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|
#define SRST_H_AHB2APB 519
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|
#define SRST_H_CENTER_BIU 520
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|
#define SRST_F_DDR_CM0_CORE 521
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|
|
|
#define SRST_DDR_TIMER0 522
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|
#define SRST_DDR_TIMER1 523
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|
#define SRST_T_WDT_DDR 524
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|
#define SRST_T_DDR_CM0_JTAG 525
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|
#define SRST_P_CENTER_GRF 526
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|
#define SRST_P_AHB2APB 527
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|
#define SRST_P_WDT 528
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|
#define SRST_P_TIMER 529
|
|
#define SRST_P_DMA2DDR 530
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|
#define SRST_P_SHAREMEM 531
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|
#define SRST_P_CENTER_BIU 532
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|
#define SRST_P_CENTER_CHANNEL_BIU 533
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|
|
|
#define SRST_P_USBDPGRF0 534
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|
#define SRST_P_USBDPPHY0 535
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|
#define SRST_P_USBDPGRF1 536
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|
#define SRST_P_USBDPPHY1 537
|
|
#define SRST_P_HDPTX0 538
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|
#define SRST_P_HDPTX1 539
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|
#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540
|
|
#define SRST_P_USB2PHY_U3_0_GRF0 541
|
|
#define SRST_P_USB2PHY_U3_1_GRF0 542
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|
#define SRST_P_USB2PHY_U2_0_GRF0 543
|
|
#define SRST_P_USB2PHY_U2_1_GRF0 544
|
|
#define SRST_HDPTX0_ROPLL 545
|
|
#define SRST_HDPTX0_LCPLL 546
|
|
#define SRST_HDPTX0 547
|
|
#define SRST_HDPTX1_ROPLL 548
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|
|
|
#define SRST_HDPTX1_LCPLL 549
|
|
#define SRST_HDPTX1 550
|
|
#define SRST_HDPTX0_HDMIRXPHY_SET 551
|
|
#define SRST_USBDP_COMBO_PHY0 552
|
|
#define SRST_USBDP_COMBO_PHY0_LCPLL 553
|
|
#define SRST_USBDP_COMBO_PHY0_ROPLL 554
|
|
#define SRST_USBDP_COMBO_PHY0_PCS_HS 555
|
|
#define SRST_USBDP_COMBO_PHY1 556
|
|
#define SRST_USBDP_COMBO_PHY1_LCPLL 557
|
|
#define SRST_USBDP_COMBO_PHY1_ROPLL 558
|
|
#define SRST_USBDP_COMBO_PHY1_PCS_HS 559
|
|
#define SRST_HDMIHDP0 560
|
|
#define SRST_HDMIHDP1 561
|
|
|
|
#define SRST_A_VO1USB_TOP_BIU 562
|
|
#define SRST_H_VO1USB_TOP_BIU 563
|
|
|
|
#define SRST_H_SDIO_BIU 564
|
|
#define SRST_H_SDIO 565
|
|
#define SRST_SDIO 566
|
|
|
|
#define SRST_H_RGA3_BIU 567
|
|
#define SRST_A_RGA3_BIU 568
|
|
#define SRST_H_RGA3_1 569
|
|
#define SRST_A_RGA3_1 570
|
|
#define SRST_RGA3_1_CORE 571
|
|
|
|
#define SRST_REF_PIPE_PHY0 572
|
|
#define SRST_REF_PIPE_PHY1 573
|
|
#define SRST_REF_PIPE_PHY2 574
|
|
|
|
#define SRST_P_PHPTOP_CRU 575
|
|
#define SRST_P_PCIE2_GRF0 576
|
|
#define SRST_P_PCIE2_GRF1 577
|
|
#define SRST_P_PCIE2_GRF2 578
|
|
#define SRST_P_PCIE2_PHY0 579
|
|
#define SRST_P_PCIE2_PHY1 580
|
|
#define SRST_P_PCIE2_PHY2 581
|
|
#define SRST_P_PCIE3_PHY 582
|
|
#define SRST_P_APB2ASB_SLV_CHIP_TOP 583
|
|
#define SRST_PCIE30_PHY 584
|
|
|
|
#define SRST_H_PMU1_BIU 585
|
|
#define SRST_P_PMU1_BIU 586
|
|
#define SRST_H_PMU_CM0_BIU 587
|
|
#define SRST_F_PMU_CM0_CORE 588
|
|
#define SRST_T_PMU1_CM0_JTAG 589
|
|
|
|
#define SRST_DDR_FAIL_SAFE 590
|
|
#define SRST_P_CRU_PMU1 591
|
|
#define SRST_P_PMU1_GRF 592
|
|
#define SRST_P_PMU1_IOC 593
|
|
#define SRST_P_PMU1WDT 594
|
|
#define SRST_T_PMU1WDT 595
|
|
#define SRST_P_PMU1TIMER 596
|
|
#define SRST_PMU1TIMER0 597
|
|
#define SRST_PMU1TIMER1 598
|
|
#define SRST_P_PMU1PWM 599
|
|
#define SRST_PMU1PWM 600
|
|
|
|
#define SRST_P_I2C0 601
|
|
#define SRST_I2C0 602
|
|
#define SRST_S_UART0 603
|
|
#define SRST_P_UART0 604
|
|
#define SRST_H_I2S1_8CH 605
|
|
#define SRST_M_I2S1_8CH_TX 606
|
|
#define SRST_M_I2S1_8CH_RX 607
|
|
#define SRST_H_PDM0 608
|
|
#define SRST_PDM0 609
|
|
|
|
#define SRST_H_VAD 610
|
|
#define SRST_HDPTX0_INIT 611
|
|
#define SRST_HDPTX0_CMN 612
|
|
#define SRST_HDPTX0_LANE 613
|
|
#define SRST_HDPTX1_INIT 614
|
|
|
|
#define SRST_HDPTX1_CMN 615
|
|
#define SRST_HDPTX1_LANE 616
|
|
#define SRST_M_MIPI_DCPHY0 617
|
|
#define SRST_S_MIPI_DCPHY0 618
|
|
#define SRST_M_MIPI_DCPHY1 619
|
|
#define SRST_S_MIPI_DCPHY1 620
|
|
#define SRST_OTGPHY_U3_0 621
|
|
#define SRST_OTGPHY_U3_1 622
|
|
#define SRST_OTGPHY_U2_0 623
|
|
#define SRST_OTGPHY_U2_1 624
|
|
|
|
#define SRST_P_PMU0GRF 625
|
|
#define SRST_P_PMU0IOC 626
|
|
#define SRST_P_GPIO0 627
|
|
#define SRST_GPIO0 628
|
|
|
|
#define SRST_A_SECURE_NS_BIU 629
|
|
#define SRST_H_SECURE_NS_BIU 630
|
|
#define SRST_A_SECURE_S_BIU 631
|
|
#define SRST_H_SECURE_S_BIU 632
|
|
#define SRST_P_SECURE_S_BIU 633
|
|
#define SRST_CRYPTO_CORE 634
|
|
|
|
#define SRST_CRYPTO_PKA 635
|
|
#define SRST_CRYPTO_RNG 636
|
|
#define SRST_A_CRYPTO 637
|
|
#define SRST_H_CRYPTO 638
|
|
#define SRST_KEYLADDER_CORE 639
|
|
#define SRST_KEYLADDER_RNG 640
|
|
#define SRST_A_KEYLADDER 641
|
|
#define SRST_H_KEYLADDER 642
|
|
#define SRST_P_OTPC_S 643
|
|
#define SRST_OTPC_S 644
|
|
#define SRST_WDT_S 645
|
|
|
|
#define SRST_T_WDT_S 646
|
|
#define SRST_H_BOOTROM 647
|
|
#define SRST_A_DCF 648
|
|
#define SRST_P_DCF 649
|
|
#define SRST_H_BOOTROM_NS 650
|
|
#define SRST_P_KEYLADDER 651
|
|
#define SRST_H_TRNG_S 652
|
|
|
|
#define SRST_H_TRNG_NS 653
|
|
#define SRST_D_SDMMC_BUFFER 654
|
|
#define SRST_H_SDMMC 655
|
|
#define SRST_H_SDMMC_BUFFER 656
|
|
#define SRST_SDMMC 657
|
|
#define SRST_P_TRNG_CHK 658
|
|
#define SRST_TRNG_S 659
|
|
|
|
#endif
|