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c2e49f706b
This patch adds support for the esd VME8349 board equipped with the MPC8349. It's a VME PMC carrier board equipped with the Tundra TSI148 VME-bridge. Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
140 lines
3.6 KiB
C
140 lines
3.6 KiB
C
/*
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* vme8349.c -- esd VME8349 board support
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*
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* Copyright (c) 2008-2009 esd gmbh.
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*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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* Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#include <asm/io.h>
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#include <asm/mmu.h>
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void ddr_enable_ecc(unsigned int dram_size);
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CONFIG_SYS_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1);
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ddr_size = ddr_size>>1, ddr_size_log2++) {
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if (ddr_size & 1)
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return -1;
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}
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
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LAWAR_SIZE);
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#if (CONFIG_SYS_DDR_SIZE == 512)
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im->ddr.csbnds[0].csbnds = 0x0000001f;
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#else
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#warning Currently any DDR size other than 512MiB is not supported
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#endif
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG | 0x00330000;
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/* currently we use only one CS, so disable the other banks */
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im->ddr.csbnds[1].csbnds = 0x00000000;
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im->ddr.csbnds[2].csbnds = 0x00000000;
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im->ddr.csbnds[3].csbnds = 0x00000000;
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im->ddr.cs_config[1] = 0;
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im->ddr.cs_config[2] = 0;
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im->ddr.cs_config[3] = 0;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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sync();
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udelay(200);
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/* enable DDR controller */
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return msize;
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}
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
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msize = fixed_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* Now check memory size (after ECC is initialized) */
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msize = get_ram_size(0, msize);
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/* return total bus SDRAM size(bytes) -- DDR */
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return msize * 1024 * 1024;
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}
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int checkboard(void)
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{
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puts("Board: esd VME8349\n");
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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}
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#endif
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