mirror of
https://github.com/AsahiLinux/u-boot
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2eab48f511
(0 = infinite) * Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on those boards that use it.
319 lines
7.4 KiB
C
319 lines
7.4 KiB
C
/*
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* The test exercises SDRAM accesses in burst mode
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*/
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#include <common.h>
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#include <exports.h>
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#include <commproc.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <serial.h>
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#include <watchdog.h>
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#include "test_burst.h"
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/* 8 MB test region of physical RAM */
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#define TEST_PADDR 0x00800000
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/* The uncached virtual region */
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#define TEST_VADDR_NC 0x00800000
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/* The cached virtual region */
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#define TEST_VADDR_C 0x01000000
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/* When an error is detected, the address where the error has been found,
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and also the current and the expected data will be written to
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the following flash address
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*/
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#define TEST_FLASH_ADDR 0x40100000
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/* Define GPIO ports to signal start of burst transfers and errors */
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#ifdef CONFIG_LWMON
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/* Use PD.8 to signal start of burst transfers */
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#define GPIO1_DAT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
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#define GPIO1_BIT 0x0080
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/* Configure PD.8 as general purpose output */
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#define GPIO1_INIT \
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((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pdpar &= ~GPIO1_BIT; \
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((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddir |= GPIO1_BIT;
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/* Use PD.9 to signal error */
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#define GPIO2_DAT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
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#define GPIO2_BIT 0x0040
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/* Configure PD.9 as general purpose output */
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#define GPIO2_INIT \
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((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pdpar &= ~GPIO2_BIT; \
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((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddir |= GPIO2_BIT;
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#endif /* CONFIG_LWMON */
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static void test_prepare (void);
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static int test_burst_start (unsigned long size, unsigned long pattern);
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static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached);
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static int test_mmu_is_on(void);
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static void test_desc(unsigned long size);
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static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern);
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static void signal_init(void);
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static void signal_start(void);
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static void signal_error(void);
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static void test_usage(void);
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static unsigned long test_pattern [] = {
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0x00000000,
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0xffffffff,
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0x55555555,
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0xaaaaaaaa,
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};
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int test_burst (int argc, char *argv[])
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{
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unsigned long size = CACHE_LINE_SIZE;
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unsigned int pass = 0;
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int res = 0;
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int i, j;
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if (argc == 3) {
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char * d;
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for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) {
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size *= 10;
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size += *d - '0';
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}
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if (size == 0 || *d) {
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test_usage();
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return 1;
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}
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for (d = argv[2]; *d >= '0' && *d <= '9'; d++) {
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pass *= 10;
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pass += *d - '0';
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}
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if (*d) {
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test_usage();
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return 1;
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}
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} else if (argc > 3) {
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test_usage();
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return 1;
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}
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size += (CACHE_LINE_SIZE - 1);
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size &= ~(CACHE_LINE_SIZE - 1);
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if (!test_mmu_is_on()) {
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test_prepare();
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}
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test_desc(size);
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for (j = 0; !pass || j < pass; j++) {
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for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]);
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i++) {
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res = test_burst_start(size, test_pattern[i]);
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if (res != 0) {
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goto Done;
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}
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}
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printf ("Iteration #%d passed\n", j + 1);
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if (tstc() && 0x03 == getc())
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break;
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}
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Done:
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return res;
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}
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static void test_prepare (void)
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{
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printf ("\n");
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caches_init();
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disable_interrupts();
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mmu_init();
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printf ("Interrupts are disabled\n");
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printf ("I-Cache is ON\n");
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printf ("D-Cache is ON\n");
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printf ("MMU is ON\n");
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printf ("\n");
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test_map_8M (TEST_PADDR, TEST_VADDR_NC, 0);
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test_map_8M (TEST_PADDR, TEST_VADDR_C, 1);
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test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0);
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/* Configure GPIO ports */
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signal_init();
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}
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static int test_burst_start (unsigned long size, unsigned long pattern)
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{
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volatile unsigned long * vaddr_c = (unsigned long *)TEST_VADDR_C;
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volatile unsigned long * vaddr_nc = (unsigned long *)TEST_VADDR_NC;
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int i, n;
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int res = 1;
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printf ("Test pattern %08x ...", pattern);
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n = size / 4;
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for (i = 0; i < n; i ++) {
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vaddr_c [i] = pattern;
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}
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signal_start();
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flush_dcache_range((unsigned long)vaddr_c, (unsigned long)(vaddr_c + n) - 1);
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for (i = 0; i < n; i ++) {
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register unsigned long tmp = vaddr_nc [i];
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if (tmp != pattern) {
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test_error("2a", vaddr_nc + i, tmp, pattern);
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goto Done;
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}
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}
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for (i = 0; i < n; i ++) {
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register unsigned long tmp = vaddr_c [i];
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if (tmp != pattern) {
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test_error("2b", vaddr_c + i, tmp, pattern);
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goto Done;
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}
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}
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for (i = 0; i < n; i ++) {
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vaddr_nc [i] = pattern;
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}
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for (i = 0; i < n; i ++) {
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register unsigned long tmp = vaddr_nc [i];
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if (tmp != pattern) {
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test_error("3a", vaddr_nc + i, tmp, pattern);
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goto Done;
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}
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}
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signal_start();
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for (i = 0; i < n; i ++) {
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register unsigned long tmp = vaddr_c [i];
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if (tmp != pattern) {
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test_error("3b", vaddr_c + i, tmp, pattern);
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goto Done;
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}
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}
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res = 0;
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Done:
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printf(" %s\n", res == 0 ? "OK" : "");
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return res;
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}
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static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached)
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{
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mtspr (MD_EPN, (vaddr & 0xFFFFFC00) | MI_EVALID);
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mtspr (MD_TWC, MI_PS8MEG | MI_SVALID);
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mtspr (MD_RPN, (paddr & 0xFFFFF000) | MI_BOOTINIT | (cached ? 0 : 2));
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mtspr (MD_AP, MI_Kp);
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}
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static int test_mmu_is_on(void)
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{
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unsigned long msr;
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asm volatile("mfmsr %0" : "=r" (msr) :);
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return msr & MSR_DR;
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}
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static void test_desc(unsigned long size)
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{
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printf(
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"The following tests will be conducted:\n"
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"1) Map %d-byte region of physical RAM at 0x%08x\n"
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" into two virtual regions:\n"
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" one cached at 0x%08x and\n"
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" the the other uncached at 0x%08x.\n",
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size, TEST_PADDR, TEST_VADDR_NC, TEST_VADDR_C);
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puts(
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"2) Fill the cached region with a pattern, and flush the cache\n"
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"2a) Check the uncached region to match the pattern\n"
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"2b) Check the cached region to match the pattern\n"
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"3) Fill the uncached region with a pattern\n"
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"3a) Check the cached region to match the pattern\n"
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"3b) Check the uncached region to match the pattern\n"
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"2b) Change the patterns and go to step 2\n"
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"\n"
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);
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}
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static void test_error(
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char * step, volatile void * addr, unsigned long val, unsigned long pattern)
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{
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volatile unsigned long * p = (void *)TEST_FLASH_ADDR;
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signal_error();
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p[0] = (unsigned long)addr;
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p[1] = val;
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p[2] = pattern;
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printf ("\nError at step %s, addr %08x: read %08x, pattern %08x",
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step, addr, val, pattern);
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}
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static void signal_init(void)
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{
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#if defined(GPIO1_INIT)
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GPIO1_INIT;
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#endif
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#if defined(GPIO2_INIT)
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GPIO2_INIT;
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#endif
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}
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static void signal_start(void)
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{
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#if defined(GPIO1_INIT)
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if (GPIO1_DAT & GPIO1_BIT) {
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GPIO1_DAT &= ~GPIO1_BIT;
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} else {
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GPIO1_DAT |= GPIO1_BIT;
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}
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#endif
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}
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static void signal_error(void)
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{
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#if defined(GPIO2_INIT)
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if (GPIO2_DAT & GPIO2_BIT) {
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GPIO2_DAT &= ~GPIO2_BIT;
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} else {
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GPIO2_DAT |= GPIO2_BIT;
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}
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#endif
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}
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static void test_usage(void)
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{
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printf("Usage: go 0x40004 [size] [count]\n");
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}
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