Rick Chen 8ba595b6bd riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL ... The mcache_ctl csr only can be manipulated in M mode. Add SPL_RISCV_MMODE for U-Boot SPL to control cache operation. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>		2019-12-10 08:23:10 +08:00
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ax25	riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL	2019-12-10 08:23:10 +08:00
generic	common: Move board_get_usable_ram_top() out of common.h	2019-12-02 18:25:04 -05:00
cpu.c	riscv: add run mode configuration for SPL	2019-08-26 16:07:42 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Return to previous privilege level after trap handling	2018-12-18 09:56:27 +08:00
start.S	riscv: update fix_rela_dyn	2019-09-03 09:30:41 +08:00
u-boot-spl.lds	riscv: add SPL support	2019-08-26 16:07:42 +08:00
u-boot.lds	riscv: Make start.S available for all targets	2018-10-03 17:48:14 +08:00