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u-boot/arch
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Rick Chen 8ba595b6bd riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL 
The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
..
arc common: Move enable/disable_interrupts out of common.h 2019-12-02 18:25:01 -05:00
arm arm: -march=armv5t for ARM11 2019-12-09 10:36:00 -05:00
m68k common: Move trap_init() out of common.h 2019-12-02 18:25:25 -05:00
microblaze common: Move enable/disable_interrupts out of common.h 2019-12-02 18:25:01 -05:00
mips Merge branch '2019-12-02-master-imports' 2019-12-02 22:05:35 -05:00
nds32 common: Move enable/disable_interrupts out of common.h 2019-12-02 18:25:01 -05:00
nios2 common: Move enable/disable_interrupts out of common.h 2019-12-02 18:25:01 -05:00
powerpc common: Move some board functions out of common.h 2019-12-02 18:25:21 -05:00
riscv riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL 2019-12-10 08:23:10 +08:00
sandbox common: Move command functions out of common.h 2019-12-02 18:25:02 -05:00
sh common: Move enable/disable_interrupts out of common.h 2019-12-02 18:25:01 -05:00
x86 x86: simplify ljmp to 32-bit code 2019-12-08 19:10:21 +08:00
xtensa common: Move interrupt functions into a new header 2019-12-02 18:25:00 -05:00
.gitignore
Kconfig sh: r2dplus: Enable OF control 2019-09-02 17:38:43 +02:00