mirror of
https://github.com/AsahiLinux/u-boot
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65 lines
2.7 KiB
C
65 lines
2.7 KiB
C
/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
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*
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* This program is used to generate definitions needed by
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* assembly language modules.
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*
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* We use the technique used in the OSF Mach kernel code:
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* generate asm statements containing #defines,
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* compile this file to assembler, and then extract the
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* #defines from the assembly-language output.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <asm/arch/mb86r0x.h>
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#include <linux/kbuild.h>
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int main(void)
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{
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/* ddr2 controller */
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DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
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DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
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DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
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DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
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DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
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DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
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DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
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DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
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DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
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DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
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DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
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DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
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DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
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DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
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DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
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/* clock reset generator */
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DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
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DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
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DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
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DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
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DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
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DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
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/* chip control module */
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DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
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/* external bus interface */
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DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
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DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
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DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
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DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
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DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
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DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
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DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
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DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
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DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
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return 0;
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}
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