mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-26 21:13:48 +00:00
221 lines
5.6 KiB
ArmAsm
221 lines
5.6 KiB
ArmAsm
#include <config.h>
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#include <version.h>
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#include <asm/arch/pxa-regs.h>
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DRAM_SIZE: .long CFG_DRAM_SIZE
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.globl memsetup
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memsetup:
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mov r10, lr
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/* ---- GPIO INITIALISATION ---- */
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/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
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/* General purpose set registers */
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ldr r0, =GPSR0
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ldr r1, =CFG_GPSR0_VAL
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str r1, [r0]
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ldr r0, =GPSR1
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ldr r1, =CFG_GPSR1_VAL
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str r1, [r0]
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ldr r0, =GPSR2
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ldr r1, =CFG_GPSR2_VAL
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str r1, [r0]
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/* General purpose clear registers */
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ldr r0, =GPCR0
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ldr r1, =CFG_GPCR0_VAL
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str r1, [r0]
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ldr r0, =GPCR1
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ldr r1, =CFG_GPCR1_VAL
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str r1, [r0]
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ldr r0, =GPCR2
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ldr r1, =CFG_GPCR2_VAL
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str r1, [r0]
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/* General rising edge registers */
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ldr r0, =GRER0
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ldr r1, =CFG_GRER0_VAL
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str r1, [r0]
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ldr r0, =GRER1
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ldr r1, =CFG_GRER1_VAL
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str r1, [r0]
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ldr r0, =GRER2
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ldr r1, =CFG_GRER2_VAL
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str r1, [r0]
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/* General falling edge registers */
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ldr r0, =GFER0
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ldr r1, =CFG_GFER0_VAL
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str r1, [r0]
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ldr r0, =GFER1
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ldr r1, =CFG_GFER1_VAL
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str r1, [r0]
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ldr r0, =GFER2
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ldr r1, =CFG_GFER2_VAL
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str r1, [r0]
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/* General edge detect registers */
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ldr r0, =GPDR0
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ldr r1, =CFG_GPDR0_VAL
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str r1, [r0]
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ldr r0, =GPDR1
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ldr r1, =CFG_GPDR1_VAL
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str r1, [r0]
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ldr r0, =GPDR2
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ldr r1, =CFG_GPDR2_VAL
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str r1, [r0]
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/* General alternate function registers */
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ldr r0, =GAFR0_L /* [0:15] */
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ldr r1, =CFG_GAFR0_L_VAL
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str r1, [r0]
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ldr r0, =GAFR0_U /* [31:16] */
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ldr r1, =CFG_GAFR0_U_VAL
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str r1, [r0]
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ldr r0, =GAFR1_L /* [47:32] */
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ldr r1, =CFG_GAFR1_L_VAL
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str r1, [r0]
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ldr r0, =GAFR1_U /* [63:48] */
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ldr r1, =CFG_GAFR1_U_VAL
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str r1, [r0]
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ldr r0, =GAFR2_L /* [79:64] */
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ldr r1, =CFG_GAFR2_L_VAL
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str r1, [r0]
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ldr r0, =GAFR2_U /* [80] */
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ldr r1, =CFG_GAFR2_U_VAL
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str r1, [r0]
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/* General purpose direction registers */
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ldr r0, =GPDR0
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ldr r1, =CFG_GPDR0_VAL
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str r1, [r0]
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ldr r0, =GPDR1
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ldr r1, =CFG_GPDR1_VAL
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str r1, [r0]
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ldr r0, =GPDR2
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ldr r1, =CFG_GPDR2_VAL
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str r1, [r0]
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/* Power manager sleep status */
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ldr r0, =PSSR
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ldr r1, =CFG_PSSR_VAL
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str r1, [r0]
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/* ---- MEMORY INITIALISATION ---- */
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/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
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/* pause for 200 uSecs- allow internal clocks to settle */
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ldr r3, =OSCR /* reset the OS Timer Count to zero */
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mov r2, #0
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str r2, [r3]
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ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */
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1:
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ldr r2, [r3]
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cmp r4, r2
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bgt 1b
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mem_init:
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/* get memory controller base address */
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ldr r1, =MEMC_BASE
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/* ---- FLASH INITIALISATION ---- */
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/* Write MSC0 and read back to ensure data change is accepted by cpu */
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ldr r2, =CFG_MSC0_VAL
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str r2, [r1, #MSC0_OFFSET]
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ldr r2, [r1, #MSC0_OFFSET]
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/* ---- SDRAM INITIALISATION ---- */
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/* get the MDREFR settings */
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ldr r2, =CFG_MDREFR_VAL
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str r2, [r1, #MDREFR_OFFSET]
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/* fetch platform value of MDCNFG */
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ldr r2, =CFG_MDCNFG_VAL
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/* disable all sdram banks */
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bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
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bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
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/* write initial value of MDCNFG, w/o enabling sdram banks */
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str r2, [r1, #MDCNFG_OFFSET]
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/* pause for 200 uSecs */
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ldr r3, =OSCR /* reset the OS Timer Count to zero */
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mov r2, #0
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str r2, [r3]
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ldr r4, =0x300 /* about 200 usec */
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1:
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ldr r2, [r3]
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cmp r4, r2
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bgt 1b
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/* Access memory *not yet enabled* for CBR refresh cycles (8) */
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/* CBR is generated for all banks */
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ldr r2, =CFG_DRAM_BASE
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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/* get memory controller base address */
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ldr r2, =MEMC_BASE
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/* Enable SDRAM bank 0 in MDCNFG register */
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ldr r2, [r1, #MDCNFG_OFFSET]
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orr r2, r2, #MDCNFG_DE0
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str r2, [r1, #MDCNFG_OFFSET]
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/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
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ldr r2, =CFG_MDMRS_VAL
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str r2, [r1, #MDMRS_OFFSET]
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/* ---- INTERRUPT INITIALISATION ---- */
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/* Disable (mask) all interrupts at the interrupt controller */
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/* clear the interrupt level register (use IRQ, not FIQ) */
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mov r1, #0
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ldr r2, =ICLR
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str r1, [r2]
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/* Set interrupt mask register */
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ldr r1, =CFG_ICMR_VAL
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ldr r2, =ICMR
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str r1, [r2]
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/* ---- CLOCK INITIALISATION ---- */
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/* Disable the peripheral clocks, and set the core clock */
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/* Turn Off ALL on-chip peripheral clocks for re-configuration */
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ldr r1, =CKEN
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mov r2, #0
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str r2, [r1]
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/* set core clocks */
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ldr r2, =CFG_CCCR_VAL
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ldr r1, =CCCR
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str r2, [r1]
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#ifdef ENABLE32KHZ
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/* enable the 32Khz oscillator for RTC and PowerManager */
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ldr r1, =OSCC
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mov r2, #OSCC_OON
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str r2, [r1]
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/* NOTE: spin here until OSCC.OOK get set, meaning the PLL has settled. */
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60:
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ldr r2, [r1]
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ands r2, r2, #1
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beq 60b
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#endif
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/* Turn on needed clocks */
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ldr r1, =CKEN
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ldr r2, =CFG_CKEN_VAL
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str r2, [r1]
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mov pc, r10
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