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dac3c6f625
This adds a new board from CS GROUP. The board is called MCR3000_2G, and has a CPU board called CMPC885. That CPU board is shared with another equipment that will be added in a later patch. That board stores Ethernet MAC addresses in an EEPROM which is accessed using SPI bus. This patch was originally written by Charles Frey who's email address is not valid anymore as he left the company. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
107 lines
3 KiB
C
107 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 CS Group
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* Charles Frey <charles.frey@c-s.fr>
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*/
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#include <common.h>
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#include <linux/sizes.h>
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#include <linux/delay.h>
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#include <init.h>
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#include <asm/io.h>
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#include <mpc8xx.h>
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define ADDR_CPLD_R_TYPE ((unsigned char __iomem *)CONFIG_CPLD_BASE + 3)
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#define _NOT_USED_ 0xFFFFEC04
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static const uint sdram_table[] = {
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/* DRAM - single read. (offset 0 in upm RAM) */
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0x0F0CEC04, 0x0FFFEC04, 0x00AF2C04, 0x0FFFEC00,
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0x0FFCE004, 0xFFFFEC05, _NOT_USED_, _NOT_USED_,
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/* DRAM - burst read. (offset 8 in upm RAM) */
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0x0F0CEC04, 0x0FFFEC04, 0x00AF2C04, 0x00FFEC00,
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0x00FFEC00, 0x00FFEC00, 0x0FFCE000, 0x1FFFEC05,
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/* DRAM - Precharge all banks. (offset 16 in upm RAM) */
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_NOT_USED_, 0x0FFCE004, 0x1FFFEC05, _NOT_USED_,
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/* DRAM - NOP. (offset 20 in upm RAM) */
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0x1FFFEC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* DRAM - single write. (offset 24 in upm RAM) */
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0x0F0CEC04, 0x0FFFEC00, 0x00AF2004, 0x0FFFEC04,
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0x0FFCE004, 0x0FFFEC04, 0xFFFFEC05, _NOT_USED_,
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/* DRAM - burst write. (offset 32 in upm RAM) */
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0x0F0CEC04, 0x0FFFEC00, 0x00AF2000, 0x00FFEC00,
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0x00FFEC00, 0x00FFEC04, 0x0FFFEC04, 0x0FFCE004,
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0x1FFFEC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* refresh (offset 48 in upm RAM) */
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0x0FFDE404, 0x0FFEAC04, 0x0FFD6C84, 0x0FFFEC04,
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0x0FFFEC04, 0x0FFFEC04, 0x0FFFEC04, 0x1FFFEC85,
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/* init (offset 56 in upm RAM) */
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0x0FEEA874, 0x0FBD6474, 0x1FFFEC45, _NOT_USED_,
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/* exception. (offset 60 in upm RAM) */
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0x0FFCE004, 0xFFFFEC05, _NOT_USED_, _NOT_USED_
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};
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/* SDRAM initialization */
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int dram_init(void)
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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memctl8xx_t __iomem *memctl = &immap->im_memctl;
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u32 max_size, mamr;
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u8 val;
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printf("UPMA init for SDRAM (CAS latency 2), ");
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printf("init address 0x%08x, size ", (int)dram_init);
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/* Verify the SDRAM size of the board */
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val = (in_8(ADDR_CPLD_R_TYPE) & 0x30) >> 4;
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if (val == 0x03 || val == 0x00) {
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max_size = 64 * SZ_1M; /* 64 Mo of SDRAM */
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mamr = 0x20104000;
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} else {
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max_size = 128 * SZ_1M; /* 128 Mo of SDRAM */
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mamr = 0x20206000;
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}
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/* Configure CS1 */
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out_be32(&memctl->memc_or1,
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~(max_size - 1) | OR_CSNT_SAM | OR_ACS_DIV2);
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out_be32(&memctl->memc_br1, CFG_SYS_SDRAM_BASE | BR_MS_UPMA | BR_V);
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/* Configure UPMA for CS1 */
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upmconfig(UPMA, (uint *)sdram_table, ARRAY_SIZE(sdram_table));
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out_be16(&memctl->memc_mptpr, MPTPR_PTP_DIV32);
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/* disable refresh */
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out_be32(&memctl->memc_mamr, mamr);
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udelay(100);
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/* NOP to maintain DQM high */
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out_be32(&memctl->memc_mcr, 0x80002114);
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udelay(200);
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out_be32(&memctl->memc_mcr, 0x80002111); /* PRECHARGE cmd */
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out_be32(&memctl->memc_mcr, 0x80002830); /* AUTO REFRESH cmd */
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out_be32(&memctl->memc_mar, 0x00000088);
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out_be32(&memctl->memc_mcr, 0x80002138);
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/* Enable refresh */
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setbits_be32(&memctl->memc_mamr, MAMR_PTAE);
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gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, max_size);
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return 0;
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}
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