u-boot/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi
Tim Harvey 4e2e2f8984 arm64: dts: imx8m{m, n}-venice-gw7902: add gpio pins for new board revision
Add gpio pins present on new board revision:
 * LTE modem support (imx8mm-gw7902 only)
  - lte_pwr#
  - lte_rst
  - lte_int
 * M2 power enable
  - m2_pwr_en
 * off-board 4.0V supply
  - vdd_4p0_en

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-01-31 18:08:23 +01:00

150 lines
2.1 KiB
Text

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Gateworks Corporation
*/
#include "imx8mn-venice-u-boot.dtsi"
&gpio1 {
m2pwren {
gpio-hog;
output-low;
gpios = <8 GPIO_ACTIVE_HIGH>;
line-name = "m2_pwren";
};
m2rst {
gpio-hog;
output-low;
gpios = <13 GPIO_ACTIVE_HIGH>;
line-name = "m2_reset";
};
m2wdis {
gpio-hog;
output-high;
gpios = <15 GPIO_ACTIVE_HIGH>;
line-name = "m2_wdis#";
};
};
&gpio2 {
uart2en {
gpio-hog;
output-high;
gpios = <8 GPIO_ACTIVE_HIGH>;
line-name = "uart2_en#";
};
};
&gpio3 {
m2gdis {
gpio-hog;
output-high;
gpios = <1 GPIO_ACTIVE_HIGH>;
line-name = "m2_gdis#";
};
m2off {
gpio-hog;
output-high;
gpios = <7 GPIO_ACTIVE_HIGH>;
line-name = "m2_off#";
};
};
&gpio4 {
appgpio1 {
gpio-hog;
input;
gpios = <21 GPIO_ACTIVE_HIGH>;
line-name = "app_gpio1";
};
vdd4p0en {
gpio-hog;
output-low;
gpios = <22 GPIO_ACTIVE_HIGH>;
line-name = "vdd_4p0_en";
};
uart1rs485 {
gpio-hog;
output-low;
gpios = <23 GPIO_ACTIVE_HIGH>;
line-name = "uart1_rs485";
};
uart1term {
gpio-hog;
output-low;
gpios = <25 GPIO_ACTIVE_HIGH>;
line-name = "uart1_term";
};
uart1half {
gpio-hog;
output-low;
gpios = <26 GPIO_ACTIVE_HIGH>;
line-name = "uart1_half";
};
appgpio2 {
gpio-hog;
input;
gpios = <27 GPIO_ACTIVE_HIGH>;
line-name = "app_gpio2";
};
mipigpio1 {
gpio-hog;
input;
gpios = <28 GPIO_ACTIVE_HIGH>;
line-name = "mipi_gpio1";
};
};
&gpio5 {
mipigpio4 {
gpio-hog;
input;
gpios = <3 GPIO_ACTIVE_HIGH>;
line-name = "mipi_gpio4";
};
mipigpio3 {
gpio-hog;
input;
gpios = <4 GPIO_ACTIVE_HIGH>;
line-name = "mipi_gpio3";
};
mipigpio2 {
gpio-hog;
input;
gpios = <5 GPIO_ACTIVE_HIGH>;
line-name = "mipi_gpio2";
};
};
&fec1 {
phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <300>;
};
&pinctrl_fec1 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};