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According to Server Base System Architecture (SBSA) specification, the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0) is for alerting the system by interrupt, the second one (WS1) is a real hardware reset. More details about the hardware specification of this device: ARM DEN0029B - Server Base System Architecture (SBSA) This driver can operate ARM SBSA Generic Watchdog as a single stage In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
34 lines
1.3 KiB
Makefile
34 lines
1.3 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-$(CONFIG_WDT_AT91) += at91sam9_wdt.o
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obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
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ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610))
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obj-y += imx_watchdog.o
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else
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obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o
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endif
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obj-$(CONFIG_S5P) += s5p_wdt.o
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obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
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obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
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obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
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obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o
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obj-$(CONFIG_$(SPL_TPL_)WDT) += wdt-uclass.o
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obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
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obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
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obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
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obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
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obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
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obj-$(CONFIG_WDT_ORION) += orion_wdt.o
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obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
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obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
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obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
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obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
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obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
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obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
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obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
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obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
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obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
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obj-$(CONFIG_WDT_XILINX) += xilinx_wwdt.o
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