mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-22 03:03:05 +00:00
2b4ffbf6b4
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE. Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
104 lines
2.7 KiB
C
104 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (C) Marvell International Ltd. and its affiliates
|
|
*/
|
|
|
|
#ifndef _DDR3_LOGGING_CONFIG_H
|
|
#define _DDR3_LOGGING_CONFIG_H
|
|
|
|
#ifdef SILENT_LIB
|
|
#define DEBUG_TRAINING_BIST_ENGINE(level, s)
|
|
#define DEBUG_TRAINING_IP(level, s)
|
|
#define DEBUG_CENTRALIZATION_ENGINE(level, s)
|
|
#define DEBUG_TRAINING_HW_ALG(level, s)
|
|
#define DEBUG_TRAINING_IP_ENGINE(level, s)
|
|
#define DEBUG_LEVELING(level, s)
|
|
#define DEBUG_PBS_ENGINE(level, s)
|
|
#define DEBUG_TRAINING_STATIC_IP(level, s)
|
|
#define DEBUG_TRAINING_ACCESS(level, s)
|
|
#else
|
|
#ifdef LIB_FUNCTIONAL_DEBUG_ONLY
|
|
#define DEBUG_TRAINING_BIST_ENGINE(level, s)
|
|
#define DEBUG_TRAINING_IP_ENGINE(level, s)
|
|
#define DEBUG_TRAINING_IP(level, s) \
|
|
if (level >= debug_training) \
|
|
printf s
|
|
#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
|
|
if (level >= debug_centralization) \
|
|
printf s
|
|
#define DEBUG_TRAINING_HW_ALG(level, s) \
|
|
if (level >= debug_training_hw_alg) \
|
|
printf s
|
|
#define DEBUG_LEVELING(level, s) \
|
|
if (level >= debug_leveling) \
|
|
printf s
|
|
#define DEBUG_PBS_ENGINE(level, s) \
|
|
if (level >= debug_pbs) \
|
|
printf s
|
|
#define DEBUG_TRAINING_STATIC_IP(level, s) \
|
|
if (level >= debug_training_static) \
|
|
printf s
|
|
#define DEBUG_TRAINING_ACCESS(level, s) \
|
|
if (level >= debug_training_access) \
|
|
printf s
|
|
#else
|
|
#define DEBUG_TRAINING_BIST_ENGINE(level, s) \
|
|
if (level >= debug_training_bist) \
|
|
printf s
|
|
|
|
#define DEBUG_TRAINING_IP_ENGINE(level, s) \
|
|
if (level >= debug_training_ip) \
|
|
printf s
|
|
#define DEBUG_TRAINING_IP(level, s) \
|
|
if (level >= debug_training) \
|
|
printf s
|
|
#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
|
|
if (level >= debug_centralization) \
|
|
printf s
|
|
#define DEBUG_TRAINING_HW_ALG(level, s) \
|
|
if (level >= debug_training_hw_alg) \
|
|
printf s
|
|
#define DEBUG_LEVELING(level, s) \
|
|
if (level >= debug_leveling) \
|
|
printf s
|
|
#define DEBUG_PBS_ENGINE(level, s) \
|
|
if (level >= debug_pbs) \
|
|
printf s
|
|
#define DEBUG_TRAINING_STATIC_IP(level, s) \
|
|
if (level >= debug_training_static) \
|
|
printf s
|
|
#define DEBUG_TRAINING_ACCESS(level, s) \
|
|
if (level >= debug_training_access) \
|
|
printf s
|
|
#endif
|
|
#endif
|
|
|
|
|
|
/* Logging defines */
|
|
enum mv_ddr_debug_level {
|
|
DEBUG_LEVEL_TRACE = 1,
|
|
DEBUG_LEVEL_INFO = 2,
|
|
DEBUG_LEVEL_ERROR = 3,
|
|
DEBUG_LEVEL_LAST
|
|
};
|
|
|
|
enum ddr_lib_debug_block {
|
|
DEBUG_BLOCK_STATIC,
|
|
DEBUG_BLOCK_TRAINING_MAIN,
|
|
DEBUG_BLOCK_LEVELING,
|
|
DEBUG_BLOCK_CENTRALIZATION,
|
|
DEBUG_BLOCK_PBS,
|
|
DEBUG_BLOCK_IP,
|
|
DEBUG_BLOCK_BIST,
|
|
DEBUG_BLOCK_ALG,
|
|
DEBUG_BLOCK_DEVICE,
|
|
DEBUG_BLOCK_ACCESS,
|
|
DEBUG_STAGES_REG_DUMP,
|
|
/* All excluding IP and REG_DUMP, should be enabled separatelly */
|
|
DEBUG_BLOCK_ALL
|
|
};
|
|
|
|
int ddr3_tip_print_log(u32 dev_num, u32 mem_addr);
|
|
int ddr3_tip_print_stability_log(u32 dev_num);
|
|
|
|
#endif /* _DDR3_LOGGING_CONFIG_H */
|