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b36df56115
This patch moves some ppc4xx related headers from the common include directory (include/) to the powerpc specific one (arch/powerpc/include/asm/). This way to common include directory is not so cluttered with files. Signed-off-by: Stefan Roese <sr@denx.de>
266 lines
9.5 KiB
ArmAsm
266 lines
9.5 KiB
ArmAsm
/******************************************************************************
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* This source code is dual-licensed. You may use it under the terms of the
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* GNU General Public License version 2, or under the license below.
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*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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* copyrights to use it in any way he or she deems fit, including
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* copying it, modifying it, compiling it, and redistributing it either
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* with or without modifications. No license under IBM patents or
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* patent applications is to be implied by the copyright license.
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*
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* Any user of this software should understand that IBM cannot provide
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* technical support for this software and will not be responsible for
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* any consequences resulting from the use of this software.
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*
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* Any person who transfers this source code or any derivative work
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* must include the IBM copyright notice, this paragraph, and the
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*
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*****************************************************************************/
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#include <config.h>
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#include <asm/ppc4xx.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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/******************************************************************************
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* Function: ext_bus_cntlr_init
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*
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* Description: Configures EBC Controller and a few basic chip selects.
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*
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* CS0 is setup to get the Boot Flash out of the addresss range
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* so that we may setup a stack. CS7 is setup so that we can
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* access and reset the hardware watchdog.
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*
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* IMPORTANT: For pass1 this code must run from
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* cache since you can not reliably change a peripheral banks
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* timing register (pbxap) while running code from that bank.
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* For ex., since we are running from ROM on bank 0, we can NOT
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* execute the code that modifies bank 0 timings from ROM, so
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* we run it from cache.
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*
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* Notes: Does NOT use the stack.
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*****************************************************************************/
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.section ".text"
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.align 2
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.globl ext_bus_cntlr_init
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.type ext_bus_cntlr_init, @function
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ext_bus_cntlr_init:
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mflr r0
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/********************************************************************
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* Prefetch entire ext_bus_cntrl_init function into the icache.
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* This is necessary because we are going to change the same CS we
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* are executing from. Otherwise a CPU lockup may occur.
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*******************************************************************/
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bl ..getAddr
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..getAddr:
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mflr r3 /* get address of ..getAddr */
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/* Calculate number of cache lines for this function */
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addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
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mtctr r4
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..ebcloop:
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icbt r0, r3 /* prefetch cache line for addr in r3*/
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addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
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bdnz ..ebcloop /* continue for $CTR cache lines */
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/********************************************************************
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* Delay to ensure all accesses to ROM are complete before changing
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* bank 0 timings. 200usec should be enough.
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* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
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*******************************************************************/
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addis r3, 0, 0x0
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ori r3, r3, 0xA000 /* wait 200us from reset */
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mtctr r3
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..spinlp:
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bdnz ..spinlp /* spin loop */
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/********************************************************************
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* Setup External Bus Controller (EBC).
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*******************************************************************/
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addi r3, 0, EBC0_CFG
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mtdcr EBC0_CFGADDR, r3
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addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */
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ori r4, r4, 0x0 /* Drive CS with external master */
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mtdcr EBC0_CFGDATA, r4
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/********************************************************************
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* Change PCIINT signal to PerWE
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*******************************************************************/
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mfdcr r4, CPC0_CR1
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ori r4, r4, 0x4000
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mtdcr CPC0_CR1, r4
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/********************************************************************
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* Memory Bank 0 (Flash Bank 0) initialization
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*******************************************************************/
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addi r3, 0, PB1AP
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mtdcr EBC0_CFGADDR, r3
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addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
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ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
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mtdcr EBC0_CFGDATA, r4
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addi r3, 0, PB0CR
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mtdcr EBC0_CFGADDR, r3
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addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
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ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
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mtdcr EBC0_CFGDATA, r4
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/********************************************************************
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* Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
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*******************************************************************/
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addi r3, 0, PB7AP
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mtdcr EBC0_CFGADDR, r3
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addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
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ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
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mtdcr EBC0_CFGDATA, r4
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addi r3, 0, PB7CR
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mtdcr EBC0_CFGADDR, r3
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addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
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ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
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mtdcr EBC0_CFGDATA, r4
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/* We are all done */
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mtlr r0 /* Restore link register */
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blr /* Return to calling function */
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.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
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/* end ext_bus_cntlr_init() */
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/******************************************************************************
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* Function: sdram_init
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*
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* Description: Configures SDRAM memory banks.
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*
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* Serial Presence Detect, "SPD," reads the SDRAM EEPROM
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* via the IIC bus and then configures the SDRAM memory
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* banks appropriately. If Auto Memory Configuration is
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* is not used, it is assumed that a 4MB 11x8x2, non-ECC,
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* SDRAM is soldered down.
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*
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* Notes: Expects that the stack is already setup.
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*****************************************************************************/
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.section ".text"
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.align 2
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.globl sdram_init
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.type sdram_init, @function
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sdram_init:
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/* save the return info on stack */
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mflr r0 /* Get link register */
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stwu r1, -8(r1) /* Save back chain and move SP */
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stw r0, +12(r1) /* Save link register */
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/*
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* First call spd_sdram to try to init SDRAM according to the
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* contents of the SPD EEPROM. If the SPD EEPROM is blank or
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* erronious, spd_sdram returns 0 in R3.
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*/
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li r3,0
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bl spd_sdram
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addic. r3, r3, 0 /* Check for error, save dram size */
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bne ..sdri_done /* If it worked, we're done... */
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/********************************************************************
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* If SPD detection fails, we'll default to 4MB, 11x8x2, as this
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* is the SMALLEST SDRAM size the 405 supports. We can do this
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* because W7O boards have soldered on RAM, and there will always
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* be some amount present. If we were using DIMMs, we should hang
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* the board instead, since it doesn't have any RAM to continue
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* running with.
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*******************************************************************/
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/*
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* Disable memory controller to allow
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* values to be changed.
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*/
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addi r3, 0, SDRAM0_CFG
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mtdcr SDRAM0_CFGADDR, r3
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addis r4, 0, 0x0
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ori r4, r4, 0x0
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mtdcr SDRAM0_CFGDATA, r4
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/*
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* Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
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* All other banks are disabled.
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*/
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addi r3, 0, SDRAM0_B0CR
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mtdcr SDRAM0_CFGADDR, r3
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addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
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ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
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mtdcr SDRAM0_CFGDATA, r4
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/* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
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addi r4, 0, 0 /* Zero the data reg */
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addi r3, r3, 4 /* Point to MB1CF reg */
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mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
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mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
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addi r3, r3, 4 /* Point to MB2CF reg */
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mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
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mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
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addi r3, r3, 4 /* Point to MB3CF reg */
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mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
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mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
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/********************************************************************
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* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
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* To set the appropriate timings, we assume sdram is
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* 100MHz (pc100 compliant).
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*******************************************************************/
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/*
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* Set up SDTR1
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*/
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addi r3, 0, SDRAM0_TR
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mtdcr SDRAM0_CFGADDR, r3
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addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
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ori r4, r4, 0x400D
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mtdcr SDRAM0_CFGDATA, r4
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/*
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* Set RTR
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*/
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addi r3, 0, SDRAM0_RTR
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mtdcr SDRAM0_CFGADDR, r3
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addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
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mtdcr SDRAM0_CFGDATA, r4
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/********************************************************************
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* Delay to ensure 200usec have elapsed since reset. Assume worst
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* case that the core is running 200Mhz:
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* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
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*******************************************************************/
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addis r3, 0, 0x0000
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ori r3, r3, 0xA000 /* Wait 200us from reset */
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mtctr r3
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..spinlp2:
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bdnz ..spinlp2 /* spin loop */
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/********************************************************************
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* Set memory controller options reg, MCOPT1.
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*******************************************************************/
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addi r3, 0, SDRAM0_CFG
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mtdcr SDRAM0_CFGADDR, r3
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addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
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ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
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mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */
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..sdri_done:
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/* restore and return */
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lwz r0, +12(r1) /* Get saved link register */
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addi r1, r1, +8 /* Remove frame from stack */
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mtlr r0 /* Restore link register */
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blr /* Return to calling function */
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.Lfe1: .size sdram_init,.Lfe1-sdram_init
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/* end sdram_init() */
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