mirror of
https://github.com/AsahiLinux/u-boot
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3f6f9d7641
Remove duplicated code in MPC8568MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
58 lines
2.2 KiB
C
58 lines
2.2 KiB
C
/*
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* Copyright 2008, 2010 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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*0) 0x0000_0000 0x7fff_ffff DDR 2G
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*1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
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*2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
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*-) 0xe000_0000 0xe00f_ffff CCSR 1M
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*3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
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*4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
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*5) 0xc000_0000 0xdfff_ffff SRIO 512MB
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*6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
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*6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
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*6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
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*6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
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*6.e) 0xfe00_0000 0xffff_ffff Flash 32MB
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*
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*Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*
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*/
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
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/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
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SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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