mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 23:47:24 +00:00
15b2d1fb72
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module based on Rockchip RK3588 from Edgeble AI. General features: - Rockchip RK3588 - up to 32GB LPDDR4x - up to 128GB eMMC - 2x MIPI CSI2 FPC On module WiFi6/BT5 is available in the following Neu6 variants. Neural Compute Module 6(Neu6) IO board is an industrial form factor ready-to-use IO board from Edgeble AI. IO board offers plenty of peripherals and connectivity options and this patch enables basic eMMC and UART which is enough to successfully boot Linux. Neu6 needs to mount on top of this IO board in order to create a complete Edgeble Neural Compute Module 6(Neu6) IO platform. Boot log for the record, DDR Version V1.08 20220617 LPDDR4X, 2112MHz channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB Manufacturer ID:0x6 CH0 RX Vref:31.7%, TX Vref:21.8%,21.8% CH1 RX Vref:30.7%, TX Vref:22.8%,23.8% CH2 RX Vref:30.7%, TX Vref:22.8%,22.8% CH3 RX Vref:30.7%, TX Vref:21.8%,21.8% change to F1: 528MHz change to F2: 1068MHz change to F3: 1560MHz change to F0: 2112MHz out U-Boot SPL 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530) Trying to boot from MMC1 INFO: Preloader serial: 2 NOTICE: BL31: v2.3():v2.3-391-g856309329:derrick.huang NOTICE: BL31: Built : 14:15:50, Jul 18 2022 INFO: ext 32k is not valid INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: system boots from cpu-hwid-0 INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001 INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz INFO: BL31: Initialising Exception Handling Framework INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa00000 INFO: SPSR = 0x3c9 U-Boot 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530) Model: Edgeble Neu6A IO Board DRAM: 7.5 GiB (effective 3.7 GiB) Core: 71 devices, 15 uclasses, devicetree: separate MMC: mmc@fe2c0000: 0 Loading Environment from nowhere... OK In: serial@feb50000 Out: serial@feb50000 Err: serial@feb50000 Model: Edgeble Neu6A IO Board Net: No ethernet found. Hit any key to stop autoboot: 0 => Add support for Edgeble Neu6 Model A IO Board. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
67 lines
1.7 KiB
Text
67 lines
1.7 KiB
Text
CONFIG_ARM=y
|
|
CONFIG_SKIP_LOWLEVEL_INIT=y
|
|
CONFIG_COUNTER_FREQUENCY=24000000
|
|
CONFIG_ARCH_ROCKCHIP=y
|
|
CONFIG_TEXT_BASE=0x00a00000
|
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|
CONFIG_NR_DRAM_BANKS=2
|
|
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
|
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
|
CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io"
|
|
CONFIG_ROCKCHIP_RK3588=y
|
|
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
|
CONFIG_SPL_MMC=y
|
|
CONFIG_SPL_SERIAL=y
|
|
CONFIG_SPL_STACK_R_ADDR=0x600000
|
|
CONFIG_TARGET_RK3588_NEU6=y
|
|
CONFIG_SPL_STACK=0x400000
|
|
CONFIG_DEBUG_UART_BASE=0xFEB50000
|
|
CONFIG_DEBUG_UART_CLOCK=24000000
|
|
CONFIG_SYS_LOAD_ADDR=0xc00800
|
|
CONFIG_DEBUG_UART=y
|
|
CONFIG_FIT=y
|
|
CONFIG_FIT_VERBOSE=y
|
|
CONFIG_SPL_LOAD_FIT=y
|
|
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6a-io.dtb"
|
|
# CONFIG_DISPLAY_CPUINFO is not set
|
|
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
|
CONFIG_SPL_MAX_SIZE=0x20000
|
|
CONFIG_SPL_PAD_TO=0x7f8000
|
|
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
|
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
|
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
|
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
|
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
|
CONFIG_SPL_STACK_R=y
|
|
CONFIG_SPL_ATF=y
|
|
CONFIG_CMD_GPT=y
|
|
CONFIG_CMD_MMC=y
|
|
# CONFIG_CMD_SETEXPR is not set
|
|
# CONFIG_SPL_DOS_PARTITION is not set
|
|
CONFIG_SPL_OF_CONTROL=y
|
|
CONFIG_OF_LIVE=y
|
|
CONFIG_NET_RANDOM_ETHADDR=y
|
|
CONFIG_SPL_REGMAP=y
|
|
CONFIG_SPL_SYSCON=y
|
|
CONFIG_SPL_CLK=y
|
|
CONFIG_ROCKCHIP_GPIO=y
|
|
CONFIG_SYS_I2C_ROCKCHIP=y
|
|
CONFIG_MISC=y
|
|
CONFIG_SUPPORT_EMMC_RPMB=y
|
|
CONFIG_MMC_DW=y
|
|
CONFIG_MMC_DW_ROCKCHIP=y
|
|
CONFIG_MMC_SDHCI=y
|
|
CONFIG_MMC_SDHCI_SDMA=y
|
|
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
|
CONFIG_ETH_DESIGNWARE=y
|
|
CONFIG_GMAC_ROCKCHIP=y
|
|
CONFIG_REGULATOR_PWM=y
|
|
CONFIG_PWM_ROCKCHIP=y
|
|
CONFIG_SPL_RAM=y
|
|
CONFIG_DM_RESET=y
|
|
CONFIG_BAUDRATE=1500000
|
|
CONFIG_DEBUG_UART_SHIFT=2
|
|
CONFIG_SYSRESET=y
|
|
# CONFIG_BINMAN_FDT is not set
|
|
CONFIG_ERRNO_STR=y
|