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https://github.com/AsahiLinux/u-boot
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9d0456822c
find_tlb_idx() is called in board_early_init_r() on multiple boards. The return value is not checked before being used to disable a TLB. In normal case the return value wouldn't be -1. In case of a mis- configuration during porting to a new board, checking the return value may be helpful to reveal some user errors. Signed-off-by: York Sun <yorksun@freescale.com>
287 lines
6.7 KiB
C
287 lines
6.7 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <hwconfig.h>
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#include <pci.h>
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#include <i2c.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_lbc.h>
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#include <asm/mp.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <ioports.h>
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#include <asm/fsl_serdes.h>
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#include <netdev.h>
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#define SYSCLK_64 64000000
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#define SYSCLK_66 66666666
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unsigned long get_board_sys_clk(ulong dummy)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
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unsigned int cpdat_val = 0;
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/* Set-up up pin muxing based on board switch settings */
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cpdat_val = par_io[1].cpdat;
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/* Check switch setting for SYSCLK select (PB3) */
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if (cpdat_val & 0x10000000)
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return SYSCLK_64;
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else
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return SYSCLK_66;
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return 0;
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}
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#ifdef CONFIG_QE
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#define PCA_IOPORT_I2C_ADDR 0x23
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#define PCA_IOPORT_OUTPUT_CMD 0x2
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#define PCA_IOPORT_CFG_CMD 0x6
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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#ifdef CONFIG_TWR_P1025
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/* GPIO */
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{1, 0, 1, 0, 0},
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{1, 18, 1, 0, 0},
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/* GPIO for switch options */
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{1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
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{1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
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{1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
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{1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
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/* QE_MUX_MDC */
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{1, 19, 1, 0, 1}, /* QE_MUX_MDC */
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/* QE_MUX_MDIO */
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{1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
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/* UCC_1_MII */
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{0, 23, 2, 0, 2}, /* CLK12 */
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{0, 24, 2, 0, 1}, /* CLK9 */
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{0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
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{0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
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{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
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{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
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{0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
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{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
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{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
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{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
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{0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
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{0, 13, 1, 0, 2}, /* ENET1_TX_ER */
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{0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
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{0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
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{0, 17, 2, 0, 2}, /* ENET1_CRS */
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{0, 16, 2, 0, 2}, /* ENET1_COL */
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/* UCC_5_RMII */
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{1, 11, 2, 0, 1}, /* CLK13 */
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{1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
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{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
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{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
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{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
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{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
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{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
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{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
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/* TDMA - clock option is configured in OS based on board setting */
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{1, 23, 2, 0, 2}, /* TDMA_TXD */
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{1, 25, 2, 0, 2}, /* TDMA_RXD */
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{1, 26, 1, 0, 2}, /* TDMA_SYNC */
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#endif
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{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
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};
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#endif
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->pmuxcr,
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(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
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/* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
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clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
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return 0;
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}
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int checkboard(void)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u8 boot_status;
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printf("Board: %s\n", CONFIG_BOARDNAME);
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boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
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puts("rom_loc: ");
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if (boot_status == PORBMSR_ROMLOC_NOR)
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puts("nor flash");
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else if (boot_status == PORBMSR_ROMLOC_SDHC)
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puts("sd");
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else
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puts("unknown");
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puts("\n");
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return 0;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
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0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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ccsr_gur_t *gur __attribute__((unused)) =
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(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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if (is_serdes_configured(SGMII_TSEC2)) {
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printf("eTSEC2 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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#if defined(CONFIG_UEC_ETH)
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/* QE0 and QE3 need to be exposed for UCC1
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* and UCC5 Eth mode (in PMUXCR register).
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* Currently QE/LBC muxed pins assumed to be
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* LBC for U-Boot and PMUXCR updated by OS if required */
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uec_standard_init(bis);
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#endif
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_QE)
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static void fdt_board_fixup_qe_pins(void *blob)
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{
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int node;
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if (!hwconfig("qe")) {
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/* For QE and eLBC pins multiplexing,
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* When don't use QE function, remove
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* qe node from dt blob.
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*/
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node = fdt_path_offset(blob, "/qe");
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if (node >= 0)
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fdt_del_node(blob, node);
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} else {
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/* For TWR Peripheral Modules - TWR-SER2
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* board only can support Signal Port MII,
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* so delete one UEC node when use MII port.
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*/
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if (hwconfig("mii"))
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node = fdt_path_offset(blob, "/qe/ucc@2400");
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else
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node = fdt_path_offset(blob, "/qe/ucc@2000");
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if (node >= 0)
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fdt_del_node(blob, node);
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}
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return;
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}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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FT_FSL_PCI_SETUP;
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#ifdef CONFIG_QE
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do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
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sizeof("okay"), 0);
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#endif
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#if defined(CONFIG_TWR_P1025)
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fdt_board_fixup_qe_pins(blob);
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#endif
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fdt_fixup_dr_usb(blob, bd);
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}
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#endif
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