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07a5cb9d3b
The prescaler value computation can yield wrong result if given 0x1f at the beginning: the value is computed to be 0x20, but the maximum value the register can hold 0x1f, so the actual stored value in this case is 0, which is obviously wrong. Set the upper bound of the value to 0x1f with the min macro. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
299 lines
6.8 KiB
C
299 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Marvell International Ltd.
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*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <spi.h>
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#include <clk.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MVEBU_SPI_A3700_XFER_RDY BIT(1)
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#define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9)
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#define MVEBU_SPI_A3700_BYTE_LEN BIT(5)
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#define MVEBU_SPI_A3700_CLK_PHA BIT(6)
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#define MVEBU_SPI_A3700_CLK_POL BIT(7)
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#define MVEBU_SPI_A3700_FIFO_EN BIT(17)
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#define MVEBU_SPI_A3700_SPI_EN_0 BIT(16)
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#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK 0x1f
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/* SPI registers */
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struct spi_reg {
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u32 ctrl; /* 0x10600 */
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u32 cfg; /* 0x10604 */
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u32 dout; /* 0x10608 */
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u32 din; /* 0x1060c */
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};
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struct mvebu_spi_platdata {
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struct spi_reg *spireg;
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struct clk clk;
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};
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static void spi_cs_activate(struct spi_reg *reg, int cs)
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{
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setbits_le32(®->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
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}
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static void spi_cs_deactivate(struct spi_reg *reg, int cs)
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{
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clrbits_le32(®->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
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}
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/**
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* spi_legacy_shift_byte() - triggers the real SPI transfer
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* @bytelen: Indicate how many bytes to transfer.
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* @dout: Buffer address of what to send.
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* @din: Buffer address of where to receive.
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*
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* This function triggers the real SPI transfer in legacy mode. It
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* will shift out char buffer from @dout, and shift in char buffer to
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* @din, if necessary.
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*
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* This function assumes that only one byte is shifted at one time.
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* However, it is not its responisbility to set the transfer type to
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* one-byte. Also, it does not guarantee that it will work if transfer
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* type becomes two-byte. See spi_set_legacy() for details.
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*
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* In legacy mode, simply write to the SPI_DOUT register will trigger
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* the transfer.
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*
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* If @dout == NULL, which means no actual data needs to be sent out,
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* then the function will shift out 0x00 in order to shift in data.
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* The XFER_RDY flag is checked every time before accessing SPI_DOUT
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* and SPI_DIN register.
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*
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* The number of transfers to be triggerred is decided by @bytelen.
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*
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* Return: 0 - cool
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* -ETIMEDOUT - XFER_RDY flag timeout
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*/
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static int spi_legacy_shift_byte(struct spi_reg *reg, unsigned int bytelen,
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const void *dout, void *din)
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{
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const u8 *dout_8;
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u8 *din_8;
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int ret;
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/* Use 0x00 as dummy dout */
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const u8 dummy_dout = 0x0;
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u32 pending_dout = 0x0;
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/* dout_8: pointer of current dout */
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dout_8 = dout;
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/* din_8: pointer of current din */
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din_8 = din;
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while (bytelen) {
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ret = wait_for_bit_le32(®->ctrl,
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MVEBU_SPI_A3700_XFER_RDY,
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true,100, false);
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if (ret)
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return ret;
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if (dout)
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pending_dout = (u32)*dout_8;
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else
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pending_dout = (u32)dummy_dout;
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/* Trigger the xfer */
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writel(pending_dout, ®->dout);
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if (din) {
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ret = wait_for_bit_le32(®->ctrl,
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MVEBU_SPI_A3700_XFER_RDY,
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true, 100, false);
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if (ret)
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return ret;
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/* Read what is transferred in */
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*din_8 = (u8)readl(®->din);
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}
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/* Don't increment the current pointer if NULL */
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if (dout)
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dout_8++;
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if (din)
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din_8++;
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bytelen--;
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}
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return 0;
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}
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static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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struct spi_reg *reg = plat->spireg;
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unsigned int bytelen;
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int ret;
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bytelen = bitlen / 8;
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if (dout && din)
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debug("This is a duplex transfer.\n");
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/* Activate CS */
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if (flags & SPI_XFER_BEGIN) {
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debug("SPI: activate cs.\n");
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spi_cs_activate(reg, spi_chip_select(dev));
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}
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/* Send and/or receive */
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if (dout || din) {
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ret = spi_legacy_shift_byte(reg, bytelen, dout, din);
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if (ret)
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return ret;
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}
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/* Deactivate CS */
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if (flags & SPI_XFER_END) {
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ret = wait_for_bit_le32(®->ctrl,
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MVEBU_SPI_A3700_XFER_RDY,
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true, 100, false);
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if (ret)
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return ret;
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debug("SPI: deactivate cs.\n");
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spi_cs_deactivate(reg, spi_chip_select(dev));
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}
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return 0;
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}
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static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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struct spi_reg *reg = plat->spireg;
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u32 data, prescale;
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data = readl(®->cfg);
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prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
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if (prescale > 0xf)
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prescale = 0x10 + (prescale + 1) / 2;
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prescale = min(prescale, 0x1fu);
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data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
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data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
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writel(data, ®->cfg);
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return 0;
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}
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static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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struct spi_reg *reg = plat->spireg;
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/*
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* Set SPI polarity
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* 0: Serial interface clock is low when inactive
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* 1: Serial interface clock is high when inactive
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*/
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if (mode & SPI_CPOL)
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setbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_POL);
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else
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clrbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_POL);
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if (mode & SPI_CPHA)
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setbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_PHA);
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else
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clrbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_PHA);
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return 0;
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}
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static int mvebu_spi_probe(struct udevice *bus)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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struct spi_reg *reg = plat->spireg;
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u32 data;
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int ret;
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/*
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* Settings SPI controller to be working in legacy mode, which
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* means use only DO pin (I/O 1) for Data Out, and DI pin (I/O 0)
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* for Data In.
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*/
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/* Flush read/write FIFO */
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data = readl(®->cfg);
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writel(data | MVEBU_SPI_A3700_FIFO_FLUSH, ®->cfg);
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ret = wait_for_bit_le32(®->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
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false, 1000, false);
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if (ret)
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return ret;
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/* Disable FIFO mode */
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data &= ~MVEBU_SPI_A3700_FIFO_EN;
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/* Always shift 1 byte at a time */
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data &= ~MVEBU_SPI_A3700_BYTE_LEN;
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writel(data, ®->cfg);
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return 0;
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}
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static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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int ret;
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plat->spireg = (struct spi_reg *)devfdt_get_addr(bus);
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ret = clk_get_by_index(bus, 0, &plat->clk);
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if (ret) {
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dev_err(bus, "cannot get clock\n");
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return ret;
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}
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return 0;
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}
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static int mvebu_spi_remove(struct udevice *bus)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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clk_free(&plat->clk);
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return 0;
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}
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static const struct dm_spi_ops mvebu_spi_ops = {
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.xfer = mvebu_spi_xfer,
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.set_speed = mvebu_spi_set_speed,
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.set_mode = mvebu_spi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static const struct udevice_id mvebu_spi_ids[] = {
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{ .compatible = "marvell,armada-3700-spi" },
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{ }
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};
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U_BOOT_DRIVER(mvebu_spi) = {
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.name = "mvebu_spi",
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.id = UCLASS_SPI,
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.of_match = mvebu_spi_ids,
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.ops = &mvebu_spi_ops,
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.ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
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.probe = mvebu_spi_probe,
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.remove = mvebu_spi_remove,
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};
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