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Wire rate IO Processor (WRIOP) provide support of receive and transmit ethernet frames from the ethernet MAC. Here Each WRIOP block supports upto 64 DPMACs. Create a house keeping data structure to support upto 16 DPMACs and store external phy related information. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
146 lines
2.5 KiB
C
146 lines
2.5 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <malloc.h>
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#include <net.h>
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#include <linux/compat.h>
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#include <asm/arch/fsl_serdes.h>
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#include <fsl-mc/ldpaa_wriop.h>
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struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
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__weak phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtc)
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{
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return PHY_INTERFACE_MODE_NONE;
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}
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void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
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{
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phy_interface_t enet_if;
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int index = dpmac_id + sd * 8;
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dpmac_info[index].enabled = 0;
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dpmac_info[index].id = 0;
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dpmac_info[index].enet_if = PHY_INTERFACE_MODE_NONE;
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enet_if = wriop_dpmac_enet_if(index, lane_prtcl);
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if (enet_if != PHY_INTERFACE_MODE_NONE) {
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dpmac_info[index].enabled = 1;
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dpmac_info[index].id = index;
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dpmac_info[index].enet_if = enet_if;
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}
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}
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/*TODO what it do */
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static int wriop_dpmac_to_index(int dpmac_id)
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{
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int i;
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for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
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if (dpmac_info[i].id == dpmac_id)
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return i;
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}
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return -1;
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}
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void wriop_disable_dpmac(int dpmac_id)
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{
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int i = wriop_dpmac_to_index(dpmac_id);
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if (i == -1)
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return;
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dpmac_info[i].enabled = 0;
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wriop_dpmac_disable(dpmac_id);
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}
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void wriop_enable_dpmac(int dpmac_id)
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{
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int i = wriop_dpmac_to_index(dpmac_id);
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if (i == -1)
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return;
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dpmac_info[i].enabled = 1;
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wriop_dpmac_enable(dpmac_id);
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}
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void wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
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{
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int i = wriop_dpmac_to_index(dpmac_id);
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if (i == -1)
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return;
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dpmac_info[i].bus = bus;
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}
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struct mii_dev *wriop_get_mdio(int dpmac_id)
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{
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int i = wriop_dpmac_to_index(dpmac_id);
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if (i == -1)
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return NULL;
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return dpmac_info[i].bus;
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}
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void wriop_set_phy_address(int dpmac_id, int address)
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{
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int i = wriop_dpmac_to_index(dpmac_id);
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if (i == -1)
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return;
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dpmac_info[i].phy_addr = address;
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}
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int wriop_get_phy_address(int dpmac_id)
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{
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int i = wriop_dpmac_to_index(dpmac_id);
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if (i == -1)
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return -1;
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return dpmac_info[i].phy_addr;
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}
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void wriop_set_phy_dev(int dpmac_id, struct phy_device *phydev)
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{
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int i = wriop_dpmac_to_index(dpmac_id);
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if (i == -1)
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return;
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dpmac_info[i].phydev = phydev;
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}
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struct phy_device *wriop_get_phy_dev(int dpmac_id)
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{
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int i = wriop_dpmac_to_index(dpmac_id);
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if (i == -1)
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return NULL;
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return dpmac_info[i].phydev;
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}
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phy_interface_t wriop_get_enet_if(int dpmac_id)
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{
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int i = wriop_dpmac_to_index(dpmac_id);
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if (i == -1)
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return PHY_INTERFACE_MODE_NONE;
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if (dpmac_info[i].enabled)
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return dpmac_info[i].enet_if;
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return PHY_INTERFACE_MODE_NONE;
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}
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