mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
c9678850bd
The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC
block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK
pad for the PHY and the same 50 MHz clock are fed back to ETHRX via
internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at
all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and
the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad
using external pad-to-pad connection.
Option (1) has two downsides. ETHCK_K is supplied directly from either
PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and
since the same PLL output is also used to supply SDMMC blocks, the
performance of SD and eMMC access is affected. The second downside is
that using this option, the EMI of the SoM is higher.
Option (2) solves both of those problems, so implement it here. In this
case, the PLL4_P is no longer limited and can be operated faster, at
100 MHz, which improves SDMMC performance (read performance is improved
from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M
count=1). The EMI interference also decreases.
Ported from Linux kernel commit
73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
372 lines
5.8 KiB
Text
372 lines
5.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2019 Marek Vasut <marex@denx.de>
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*/
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-u-boot.dtsi"
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#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
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#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
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#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
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/ {
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aliases {
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i2c1 = &i2c2;
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i2c3 = &i2c4;
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i2c4 = &i2c5;
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mmc0 = &sdmmc1;
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mmc1 = &sdmmc2;
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spi0 = &qspi;
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usb0 = &usbotg_hs;
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eeprom0 = &eeprom0;
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};
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config {
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u-boot,boot-led = "heartbeat";
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u-boot,error-led = "error";
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dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
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dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
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};
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};
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ðernet0 {
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phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
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/delete-property/ st,eth-ref-clk-sel;
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};
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ðernet0_rmii_pins_a {
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pins1 {
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pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
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<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
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<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
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<STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
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<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
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<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
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};
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};
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&i2c4 {
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bootph-all;
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bootph-pre-ram;
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eeprom0: eeprom@50 {
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};
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};
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&i2c4_pins_a {
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bootph-all;
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pins {
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bootph-all;
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};
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};
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&phy0 {
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/delete-property/ reset-gpios;
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};
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&pinctrl {
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mco2_pins_a: mco2-0 {
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pins {
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pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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mco2_sleep_pins_a: mco2-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
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};
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};
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};
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&pmic {
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bootph-all;
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bootph-pre-ram;
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regulators {
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bootph-pre-ram;
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};
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};
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&flash0 {
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bootph-pre-ram;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "fsbl1";
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reg = <0x00000000 0x00040000>;
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};
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partition@40000 {
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label = "fsbl2";
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reg = <0x00040000 0x00040000>;
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};
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partition@500000 {
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label = "uboot";
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reg = <0x00080000 0x00160000>;
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};
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partition@900000 {
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label = "env1";
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reg = <0x001E0000 0x00010000>;
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};
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partition@980000 {
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label = "env2";
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reg = <0x001F0000 0x00010000>;
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};
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};
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};
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&qspi {
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bootph-pre-ram;
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};
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&qspi_clk_pins_a {
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bootph-pre-ram;
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pins {
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bootph-pre-ram;
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};
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};
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&qspi_bk1_pins_a {
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bootph-pre-ram;
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pins1 {
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bootph-pre-ram;
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};
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pins2 {
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bootph-pre-ram;
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};
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};
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&qspi_bk2_pins_a {
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bootph-pre-ram;
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pins1 {
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bootph-pre-ram;
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};
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pins2 {
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bootph-pre-ram;
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};
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};
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&rcc {
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/*
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* Reinstate clock names from stm32mp151.dtsi, the MCO2 trick
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* used in stm32mp15xx-dhcom-som.dtsi is not supported by the
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* U-Boot clock framework.
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*/
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clock-names = "hse", "hsi", "csi", "lse", "lsi";
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clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
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<&clk_lse>, <&clk_lsi>;
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/* The MCO2 is already configured correctly, remove those. */
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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/delete-property/ assigned-clock-rates;
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_PLL4P
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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1 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_PLL4P
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL4P
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSE
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4R
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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CLK_SAI4_PLL3Q
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CLK_RNG1_LSI
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CLK_RNG2_LSI
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CLK_LPTIM1_PCLK1
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CLK_LPTIM23_PCLK3
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CLK_LPTIM45_LSE
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>;
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/*
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* cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
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* frac = < f >;
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*
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* PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
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* DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
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* m ... for PLL1,2: m=2 ; for PLL3,4: m=1
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* XTAL = 24 MHz
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*
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* VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
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* P = VCO / (P + 1)
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* Q = VCO / (Q + 1)
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* R = VCO / (R + 1)
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*/
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
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pll2: st,pll@1 {
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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cfg = < 2 65 1 0 0 PQR(1,1,1) >;
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frac = < 0x1400 >;
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bootph-all;
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};
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
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pll3: st,pll@2 {
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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cfg = < 1 33 1 16 36 PQR(1,1,1) >;
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frac = < 0x1a04 >;
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bootph-all;
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};
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/* VCO = 600.0 MHz => P = 100, Q = 50, R = 50 */
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pll4: st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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cfg = < 1 49 5 11 11 PQR(1,1,1) >;
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bootph-all;
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};
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};
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&sdmmc1 {
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bootph-pre-ram;
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st,use-ckin;
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st,cmd-gpios = <&gpiod 2 0>;
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st,ck-gpios = <&gpioc 12 0>;
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st,ckin-gpios = <&gpioe 4 0>;
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};
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&sdmmc1_b4_pins_a {
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bootph-pre-ram;
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pins1 {
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bootph-pre-ram;
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};
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pins2 {
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bootph-pre-ram;
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};
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};
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&sdmmc1_dir_pins_a {
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bootph-pre-ram;
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pins1 {
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bootph-pre-ram;
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};
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pins2 {
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bootph-pre-ram;
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};
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};
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&sdmmc2 {
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bootph-pre-ram;
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};
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&sdmmc2_b4_pins_a {
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bootph-pre-ram;
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pins {
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bootph-pre-ram;
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};
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};
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&sdmmc2_d47_pins_a {
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bootph-pre-ram;
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pins {
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bootph-pre-ram;
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};
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};
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&uart4 {
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bootph-all;
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};
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&uart4_pins_a {
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bootph-all;
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pins1 {
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bootph-all;
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};
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pins2 {
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bootph-all;
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/* pull-up on rx to avoid floating level */
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bias-pull-up;
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};
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};
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®11 {
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bootph-pre-ram;
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};
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®18 {
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bootph-pre-ram;
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};
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&usb33 {
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bootph-pre-ram;
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};
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&usbotg_hs_pins_a {
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bootph-pre-ram;
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};
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&usbotg_hs {
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bootph-pre-ram;
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};
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&usbphyc {
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bootph-pre-ram;
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};
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&usbphyc_port0 {
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bootph-pre-ram;
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};
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&usbphyc_port1 {
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bootph-pre-ram;
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};
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&vdd_usb {
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bootph-pre-ram;
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};
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