mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 14:23:00 +00:00
52923c6db7
AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
7 lines
184 B
Makefile
7 lines
184 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
# Copyright (C) 2017 Andes Technology Corporation
|
|
# Rick Chen, Andes Technology Corporation <rick@andestech.com>
|
|
|
|
obj-y := cpu.o
|
|
obj-y += cache.o
|