mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 23:47:24 +00:00
bc824cc03a
To use it with the DM timer driver in SPL and TPL, timer0 needs to be marked as pre-reloc. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
93 lines
1.6 KiB
Text
93 lines
1.6 KiB
Text
/*
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+ X11
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*/
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/ {
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config {
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u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
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u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
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};
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chosen {
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stdout-path = "serial0:115200n8";
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u-boot,spl-boot-order = &emmc, &sdmmc;
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};
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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};
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&service_msch {
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u-boot,dm-pre-reloc;
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};
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&dmc {
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u-boot,dm-pre-reloc;
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/*
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* Validation of throughput using SPEC2000 shows the following
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* relative performance for the different memory schedules:
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* - CBDR: 30.1
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* - CBRD: 29.8
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* - CRBD: 29.9
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* Note that the best performance for any given application workload
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* may vary from the default configured here (e.g. 164.gzip is fastest
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* with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
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*
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* See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
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* details on the 'rockchip,memory-schedule' property and how it
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* affects the physical-address to device-address mapping.
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*/
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rockchip,memory-schedule = <DMC_MSCH_CBDR>;
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rockchip,ddr-frequency = <800000000>;
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rockchip,ddr-speed-bin = <DDR3_1600K>;
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status = "okay";
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};
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&pmugrf {
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u-boot,dm-pre-reloc;
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};
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&sgrf {
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u-boot,dm-pre-reloc;
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};
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&cru {
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u-boot,dm-pre-reloc;
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};
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&grf {
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u-boot,dm-pre-reloc;
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};
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&uart0 {
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u-boot,dm-pre-reloc;
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};
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&emmc {
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u-boot,dm-pre-reloc;
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};
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&sdmmc {
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u-boot,dm-pre-reloc;
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};
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&spi1 {
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u-boot,dm-pre-reloc;
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spiflash: w25q32dw@0 {
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u-boot,dm-pre-reloc;
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};
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};
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&timer0 {
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u-boot,dm-pre-reloc;
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clock-frequency = <24000000>;
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};
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