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c202426d6a
Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
94 lines
2.3 KiB
C
94 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 StarFive, Inc. All rights reserved.
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* Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <time.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <dm/device-internal.h>
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#include <linux/err.h>
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#define STF_TIMER_INT_STATUS 0x00
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#define STF_TIMER_CTL 0x04
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#define STF_TIMER_LOAD 0x08
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#define STF_TIMER_ENABLE 0x10
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#define STF_TIMER_RELOAD 0x14
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#define STF_TIMER_VALUE 0x18
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#define STF_TIMER_INT_CLR 0x20
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#define STF_TIMER_INT_MASK 0x24
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struct starfive_timer_priv {
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void __iomem *base;
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u32 timer_size;
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};
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static u64 notrace starfive_get_count(struct udevice *dev)
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{
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struct starfive_timer_priv *priv = dev_get_priv(dev);
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/* Read decrement timer value and convert to increment value */
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return priv->timer_size - readl(priv->base + STF_TIMER_VALUE);
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}
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static const struct timer_ops starfive_ops = {
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.get_count = starfive_get_count,
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};
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static int starfive_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct starfive_timer_priv *priv = dev_get_priv(dev);
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int timer_channel;
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struct clk clk;
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int ret;
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priv->base = dev_read_addr_ptr(dev);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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timer_channel = dev_read_u32_default(dev, "channel", 0);
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priv->base = priv->base + (0x40 * timer_channel);
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/* Get clock rate from channel selectecd*/
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ret = clk_get_by_index(dev, timer_channel, &clk);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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uc_priv->clock_rate = clk_get_rate(&clk);
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/* Initiate timer, channel 0 */
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/* Unmask Interrupt Mask */
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writel(0, priv->base + STF_TIMER_INT_MASK);
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/* Single run mode Setting */
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if (dev_read_bool(dev, "single-run"))
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writel(1, priv->base + STF_TIMER_CTL);
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/* Set Reload value */
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priv->timer_size = dev_read_u32_default(dev, "timer-size", 0xffffffff);
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writel(priv->timer_size, priv->base + STF_TIMER_LOAD);
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/* Enable to start timer */
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writel(1, priv->base + STF_TIMER_ENABLE);
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return 0;
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}
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static const struct udevice_id starfive_ids[] = {
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{ .compatible = "starfive,jh8100-timers" },
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{ }
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};
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U_BOOT_DRIVER(jh8100_starfive_timer) = {
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.name = "jh8100_starfive_timer",
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.id = UCLASS_TIMER,
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.of_match = starfive_ids,
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.probe = starfive_probe,
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.ops = &starfive_ops,
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.priv_auto = sizeof(struct starfive_timer_priv),
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};
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