mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
11381fba99
The commit 0dba45864b ("arm: Init the debug UART") calls
debug_uart_init() from crt0.S but it won't work because SOC is not
configured yet. That's why create board_debug_uart_init() which calls
psu_init() via new psu_uboot_init() earlier before the first access to UART
in SPL. In full U-Boot call psu_uboot_init() only when
CONFIG_ZYNQMP_PSU_INIT_ENABLED is enabled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/878dc2daaa8685346f889989fbfb98b2e44da7fb.1645104518.git.michal.simek@xilinx.com
135 lines
2.7 KiB
C
135 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 - 2016 Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/spl.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/ecc_spl_init.h>
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#include <asm/arch/psu_init_gpl.h>
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#include <asm/arch/sys_proto.h>
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#if defined(CONFIG_DEBUG_UART_BOARD_INIT)
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void board_debug_uart_init(void)
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{
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psu_uboot_init();
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}
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#endif
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void board_init_f(ulong dummy)
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{
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#if !defined(CONFIG_DEBUG_UART_BOARD_INIT)
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psu_uboot_init();
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#endif
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board_early_init_r();
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#ifdef CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT
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zynqmp_ecc_init();
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#endif
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}
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static void ps_mode_reset(ulong mode)
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{
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writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
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&crlapb_base->boot_pin_ctrl);
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udelay(5);
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writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
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mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
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&crlapb_base->boot_pin_ctrl);
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}
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/*
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* Set default PS_MODE1 which is used for USB ULPI phy reset
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* Also other resets can be connected to this certain pin
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*/
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#ifndef MODE_RESET
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# define MODE_RESET PS_MODE1
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#endif
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#ifdef CONFIG_SPL_BOARD_INIT
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void spl_board_init(void)
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{
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preloader_console_init();
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ps_mode_reset(MODE_RESET);
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board_init();
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psu_post_config_data();
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}
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#endif
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = spl_boot_device();
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if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
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spl_boot_list[1] = BOOT_DEVICE_MMC2;
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if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
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spl_boot_list[1] = BOOT_DEVICE_MMC1;
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spl_boot_list[2] = BOOT_DEVICE_RAM;
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}
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u32 spl_boot_device(void)
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{
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u32 reg = 0;
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u8 bootmode;
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#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
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/* Change default boot mode at run-time */
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writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
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&crlapb_base->boot_mode);
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#endif
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reg = readl(&crlapb_base->boot_mode);
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if (reg >> BOOT_MODE_ALT_SHIFT)
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reg >>= BOOT_MODE_ALT_SHIFT;
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bootmode = reg & BOOT_MODES_MASK;
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switch (bootmode) {
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case JTAG_MODE:
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return BOOT_DEVICE_RAM;
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#ifdef CONFIG_SPL_MMC
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case SD_MODE1:
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case SD1_LSHFT_MODE: /* not working on silicon v1 */
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return BOOT_DEVICE_MMC2;
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case SD_MODE:
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case EMMC_MODE:
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return BOOT_DEVICE_MMC1;
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#endif
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#ifdef CONFIG_SPL_DFU
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case USB_MODE:
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return BOOT_DEVICE_DFU;
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#endif
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#ifdef CONFIG_SPL_SATA
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case SW_SATA_MODE:
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return BOOT_DEVICE_SATA;
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#endif
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#ifdef CONFIG_SPL_SPI
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case QSPI_MODE_24BIT:
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case QSPI_MODE_32BIT:
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return BOOT_DEVICE_SPI;
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#endif
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default:
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printf("Invalid Boot Mode:0x%x\n", bootmode);
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break;
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}
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return 0;
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}
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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return 0;
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}
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#endif
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