mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
590cee8315
At present the mtrr functions disable the cache before making changes and enable it again afterwards. This is fine in U-Boot, but does not work if running in CAR (such as we are in SPL). Update the functions so that the caller can request that caches be left alone. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
138 lines
3.1 KiB
C
138 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 Google, Inc
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*/
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#include <common.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
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"Uncacheable",
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"Combine",
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"2",
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"3",
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"Through",
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"Protect",
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"Back",
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};
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static int do_mtrr_list(void)
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{
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int i;
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printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||",
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"Mask ||", "Size ||");
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for (i = 0; i < MTRR_COUNT; i++) {
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const char *type = "Invalid";
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uint64_t base, mask, size;
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bool valid;
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base = native_read_msr(MTRR_PHYS_BASE_MSR(i));
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mask = native_read_msr(MTRR_PHYS_MASK_MSR(i));
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size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
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size |= (1 << 12) - 1;
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size += 1;
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valid = mask & MTRR_PHYS_MASK_VALID;
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type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
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printf("%d %-5s %-12s %016llx %016llx %016llx\n", i,
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valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
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mask & ~MTRR_PHYS_MASK_VALID, size);
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}
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return 0;
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}
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static int do_mtrr_set(uint reg, int argc, char * const argv[])
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{
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const char *typename = argv[0];
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struct mtrr_state state;
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uint32_t start, size;
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uint64_t base, mask;
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int i, type = -1;
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bool valid;
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if (argc < 3)
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return CMD_RET_USAGE;
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for (i = 0; i < MTRR_TYPE_COUNT; i++) {
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if (*typename == *mtrr_type_name[i])
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type = i;
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}
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if (type == -1) {
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printf("Invalid type name %s\n", typename);
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return CMD_RET_USAGE;
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}
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start = simple_strtoul(argv[1], NULL, 16);
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size = simple_strtoul(argv[2], NULL, 16);
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base = start | type;
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valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID;
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mask = ~((uint64_t)size - 1);
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mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
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if (valid)
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mask |= MTRR_PHYS_MASK_VALID;
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printf("base=%llx, mask=%llx\n", base, mask);
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mtrr_open(&state, true);
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wrmsrl(MTRR_PHYS_BASE_MSR(reg), base);
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wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
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mtrr_close(&state, true);
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return 0;
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}
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static int mtrr_set_valid(int reg, bool valid)
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{
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struct mtrr_state state;
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uint64_t mask;
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mtrr_open(&state, true);
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mask = native_read_msr(MTRR_PHYS_MASK_MSR(reg));
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if (valid)
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mask |= MTRR_PHYS_MASK_VALID;
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else
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mask &= ~MTRR_PHYS_MASK_VALID;
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wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
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mtrr_close(&state, true);
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return 0;
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}
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static int do_mtrr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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const char *cmd;
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uint reg;
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cmd = argv[1];
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if (argc < 2 || *cmd == 'l')
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return do_mtrr_list();
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argc -= 2;
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argv += 2;
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if (argc <= 0)
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return CMD_RET_USAGE;
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reg = simple_strtoul(argv[0], NULL, 16);
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if (reg >= MTRR_COUNT) {
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printf("Invalid register number\n");
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return CMD_RET_USAGE;
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}
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if (*cmd == 'e')
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return mtrr_set_valid(reg, true);
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else if (*cmd == 'd')
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return mtrr_set_valid(reg, false);
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else if (*cmd == 's')
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return do_mtrr_set(reg, argc - 1, argv + 1);
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else
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return CMD_RET_USAGE;
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return 0;
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}
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U_BOOT_CMD(
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mtrr, 6, 1, do_mtrr,
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"Use x86 memory type range registers (32-bit only)",
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"[list] - list current registers\n"
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"set <reg> <type> <start> <size> - set a register\n"
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"\t<type> is Uncacheable, Combine, Through, Protect, Back\n"
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"disable <reg> - disable a register\n"
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"ensable <reg> - enable a register"
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);
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