Leo Yu-Chi Liang 61d5c543f3 andes: cpu: Enable cache and TLB ECC support ... Andes CPU supports cache and TLB ECC. Enable them by default. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>		2023-12-27 17:29:07 +08:00
..
arch-andes	andes: cpu: Enable cache and TLB ECC support	2023-12-27 17:29:07 +08:00
arch-fu540	board: sifive: use ccache driver instead of helper function	2021-09-07 10:34:29 +08:00
arch-fu740	include: Remove unused header files	2023-05-31 12:31:47 -04:00
arch-generic	dm: treewide: Rename ..._platdata variables to just ..._plat	2020-12-13 16:51:09 -07:00
arch-jh7110	riscv: cpu: jh7110: Add gpio helper macros	2023-11-02 15:44:56 +08:00
acpi_table.h	acpi: Add missing RISC-V acpi_table header	2023-08-02 11:02:33 +08:00
asm.h	riscv: Sync csr.h with Linux kernel v5.2	2019-08-15 13:42:28 +08:00
atomic.h	riscv: add generic link for <asm/atomic.h>	2023-07-06 17:28:08 +08:00
barrier.h	riscv: make use of the barrier functions from Linux	2018-11-26 13:57:30 +08:00
bitops.h	riscv: define test_and_{set,clear}_bit in asm/bitops.h	2023-07-06 17:28:08 +08:00
byteorder.h	riscv: nx25: include: Add header files to support RISC-V	2018-01-12 08:05:12 -05:00
cache.h	riscv: lib: modify the indent	2021-09-07 10:34:29 +08:00
config.h	Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig	2022-07-07 14:01:09 -04:00
csr.h	andes: csr.h: Clean up CSR definition	2023-12-27 17:29:07 +08:00
dma-mapping.h	riscv: Remove common.h usage	2023-10-24 16:34:45 -04:00
encoding.h	global: Finish CONFIG -> CFG migration	2023-01-20 12:27:24 -05:00
global_data.h	global: Rework architecture global_data.h to include <linux/types.h>	2023-12-21 08:54:37 -05:00
gpio.h	gpio: sifive: add support for DM based gpio driver for FU540-SoC	2019-10-18 09:04:01 +08:00
io.h	riscv: io.h: Fix signatures of reads/writes functions	2023-11-28 16:19:06 -05:00
linkage.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
posix_types.h	riscv: fix use of incorrectly sized variables	2018-11-26 13:57:29 +08:00
processor.h	riscv: nx25: include: Add header files to support RISC-V	2018-01-12 08:05:12 -05:00
ptrace.h	riscv: checkpatch: Fix alignment should match open parenthesis	2018-03-30 13:13:22 +08:00
sbi.h	risc-v: implement DBCN write byte	2023-09-05 10:53:55 +08:00
sections.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
setjmp.h	SPDX: Convert single license tags to Linux Kernel style	2018-05-29 14:44:21 +08:00
smp.h	riscv: Remove common.h usage	2023-10-24 16:34:45 -04:00
spl.h	common: spl: Add spl NVMe boot support	2023-06-19 17:47:41 -04:00
string.h	riscv: Add Zbb support for building U-Boot	2023-10-19 17:29:50 +08:00
syscon.h	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
system.h	event: Convert existing spy records to simple	2023-08-31 13:16:54 -04:00
types.h	riscv: Change phys_addr_t and phys_size_t to 64-bit	2021-02-03 03:38:41 -07:00
u-boot-riscv.h	riscv: Provide a mechanism to fix DT for reserved memory	2020-04-23 10:14:16 +08:00
u-boot.h	bdinfo: riscv: Use generic bd_info	2020-06-25 13:24:10 -04:00
unaligned.h	riscv: nx25: include: Add header files to support RISC-V	2018-01-12 08:05:12 -05:00