mirror of
https://github.com/AsahiLinux/u-boot
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88ebf5830f
Add a PL310 cache controller driver that is usually found on ARMv7(32-bit) devices. The driver configures the cache settings that can be found in the device tree files. This initial revision only configures basic settings(data & instruction prefetch, shared-override, data & tag latency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
76 lines
1.9 KiB
C
76 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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static void l2c310_of_parse_and_init(struct udevice *dev)
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{
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u32 tag[3] = { 0, 0, 0 };
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u32 saved_reg, prefetch;
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struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
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/* Disable the L2 Cache */
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clrbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
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saved_reg = readl(®s->pl310_aux_ctrl);
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if (!dev_read_u32(dev, "prefetch-data", &prefetch)) {
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if (prefetch)
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saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
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else
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saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
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}
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if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) {
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if (prefetch)
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saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
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else
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saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
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}
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saved_reg |= dev_read_bool(dev, "arm,shared-override");
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writel(saved_reg, ®s->pl310_aux_ctrl);
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saved_reg = readl(®s->pl310_tag_latency_ctrl);
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if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
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saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
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L310_LATENCY_CTRL_WR(tag[1] - 1) |
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L310_LATENCY_CTRL_SETUP(tag[2] - 1);
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writel(saved_reg, ®s->pl310_tag_latency_ctrl);
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saved_reg = readl(®s->pl310_data_latency_ctrl);
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if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
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saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
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L310_LATENCY_CTRL_WR(tag[1] - 1) |
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L310_LATENCY_CTRL_SETUP(tag[2] - 1);
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writel(saved_reg, ®s->pl310_data_latency_ctrl);
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/* Enable the L2 cache */
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setbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
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}
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static int l2x0_probe(struct udevice *dev)
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{
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l2c310_of_parse_and_init(dev);
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return 0;
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}
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static const struct udevice_id l2x0_ids[] = {
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{ .compatible = "arm,pl310-cache" },
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{}
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};
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U_BOOT_DRIVER(pl310_cache) = {
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.name = "pl310_cache",
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.id = UCLASS_CACHE,
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.of_match = l2x0_ids,
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.probe = l2x0_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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