mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-17 08:43:07 +00:00
e26416a3f1
T1024RDB-PB board adds 2.5G SGMII support with AQR105 PHY. rcw_0x095 is used for 10G XFI + 3x PCIex1 rcw_0x135 is used for 2.5G SGMII + 2x PCIex1 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
49 lines
1.8 KiB
C
49 lines
1.8 KiB
C
/**
|
|
* Copyright 2014 Freescale Semiconductor
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*
|
|
*/
|
|
|
|
struct cpld_data {
|
|
u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
|
|
u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
|
|
u8 hw_ver; /* 0x02 - Hardware Revision Register */
|
|
u8 sw_ver; /* 0x03 - Software Revision register */
|
|
u8 res0[12]; /* 0x04 - 0x0F - not used */
|
|
u8 reset_ctl1; /* 0x10 - Reset control Register1 */
|
|
u8 reset_ctl2; /* 0x11 - Reset control Register2 */
|
|
u8 int_status; /* 0x12 - Interrupt status Register */
|
|
u8 flash_csr; /* 0x13 - Flash control and status register */
|
|
u8 fan_ctl_status; /* 0x14 - Fan control and status register */
|
|
u8 led_ctl_status; /* 0x15 - LED control and status register */
|
|
u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
|
|
u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
|
|
u8 boot_override; /* 0x18 - Boot override register */
|
|
u8 boot_config1; /* 0x19 - Boot config override register*/
|
|
u8 boot_config2; /* 0x1A - Boot config override register*/
|
|
} cpld_data_t;
|
|
|
|
|
|
/* Pointer to the CPLD register set */
|
|
|
|
u8 cpld_read(unsigned int reg);
|
|
void cpld_write(unsigned int reg, u8 value);
|
|
|
|
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
|
|
#define CPLD_WRITE(reg, value)\
|
|
cpld_write(offsetof(struct cpld_data, reg), value)
|
|
|
|
/* CPLD on IFC */
|
|
#define CPLD_LBMAP_MASK 0x3F
|
|
#define CPLD_BANK_SEL_MASK 0x07
|
|
#define CPLD_BANK_OVERRIDE 0x40
|
|
#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
|
|
#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
|
|
#define CPLD_LBMAP_RESET 0xFF
|
|
#define CPLD_LBMAP_SHIFT 0x03
|
|
#define CPLD_BOOT_SEL 0x80
|
|
|
|
#define CPLD_PCIE_SGMII_MUX 0x80
|
|
#define CPLD_OVERRIDE_BOOT_EN 0x01
|
|
#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */
|