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https://github.com/AsahiLinux/u-boot
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656e6cc86b
Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
270 lines
8.3 KiB
Text
270 lines
8.3 KiB
Text
Functions of Armada CP110 pin controller
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Function 0x0 for any MPP ID activates GPIO pin mode
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Function 0xc for any MPP ID activates DEBUG_BUS pin mode
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-------------------------------------------------------------------------------
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MPP# 0x1 0x2 0x3 0x4
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-------------------------------------------------------------------------------
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0 DEV_ALE[1] AU_I2SMCLK GE0_RXD[3] TDM_PCLK
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1 DEV_ALE[0] AU_I2SDO_SPDIFO GE0_RXD[2] TDM_DRX
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2 DEV_AD[15] AU_I2SEXTCLK GE0_RXD[1] TDM_DTX
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3 DEV_AD[14] AU_I2SLRCLK GE0_RXD[0] TDM_FSYNC
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4 DEV_AD[13] AU_I2SBCLK GE0_RXCTL TDM_RSTn
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5 DEV_AD[12] AU_I2SDI GE0_RXCLK TDM_INTn
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6 DEV_AD[11] - GE0_TXD[3] SPI0_CSn[2]
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7 DEV_AD[10] - GE0_TXD[2] SPI0_CSn[1]
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8 DEV_AD[9] - GE0_TXD[1] SPI0_CSn[0]
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9 DEV_AD[8] - GE0_TXD[0] SPI0_MOSI
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10 DEV_READYn - GE0_TXCTL SPI0_MISO
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11 DEV_WEn[1] - GE0_TXCLKOUT SPI0_CLK
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12 DEV_CLK_OUT NF_RBn[1] SPI1_CSn[1] GE0_RXCLK
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13 DEV_BURSTn NF_RBn[0] SPI1_MISO GE0_RXCTL
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14 DEV_BOOTCSn DEV_CSn[0] SPI1_CSn[0] SPI0_CSn[3]
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15 DEV_AD[7] - SPI1_MOSI -
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16 DEV_AD[6] - SPI1_CLK -
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17 DEV_AD[5] - - GE0_TXD[3]
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18 DEV_AD[4] - - GE0_TXD[2]
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19 DEV_AD[3] - - GE0_TXD[1]
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20 DEV_AD[2] - - GE0_TXD[0]
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21 DEV_AD[1] - - GE0_TXCTL
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22 DEV_AD[0] - - GE0_TXCLKOUT
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23 DEV_A[1] - - -
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24 DEV_A[0] - - -
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25 DEV_OEn - - - -
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26 DEV_WEn[0] - - -
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27 DEV_CSn[0] SPI1_MISO MSS_GPIO[4] GE0_RXD[3]
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28 DEV_CSn[1] SPI1_CSn[0] MSS_GPIO[5] GE0_RXD[2]
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29 DEV_CSn[2] SPI1_MOSI MSS_GPIO[6] GE0_RXD[1]
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30 DEV_CSn[3] SPI1_CLK MSS_GPIO[7] GE0_RXD[0]
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31 DEV_A[2] - MSS_GPIO[4] -
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32 MII_COL MII_TXERR MSS_SPI_MISO TDM_DRX
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33 MII_TXCLK SDIO_PWR1[0] MSS_SPI_CSn TDM_FSYNC
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34 MII_RXERR SDIO_PWR1[1] MSS_SPI_MOSI TDM_DTX
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35 SATA1_PRESENT_ACTIVEn TWSI1_SDA MSS_SPI_CLK TDM_PCLK
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36 SYNCE2_CLK TWSI1_SCK PTP_CLK SYNCE1_CLK
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37 UART2_RXD TWSI0_SCK PTP_PCLK_OUT TDM_INTn
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38 UART2_TXD TWSI0_SDA PTP_PULSE TDM_RSTn
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39 SDIO_WR_PROTECT - - AU_I2SBCLK PTP_CLK
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40 SDIO_PWR1[1] SYNCE1_CLK MSS_TWSI_SDA AU_I2SDO_SPDIFO
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41 SDIO_PWR1[0] SDIO_BUS_PWR MSS_TWSI_SCK AU_I2SLRCLK
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42 SDIO_V18_EN SDIO_WR_PROTECT SYNCE2_CLK AU_I2SMCLK
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43 SDIO_CARD_DETECT - SYNCE1_CLK AU_I2SEXTCLK
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44 GE1_TXD[2] - - -
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45 GE1_TXD[3] - - -
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46 GE1_TXD[1] - - -
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47 GE1_TXD[0] - - -
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48 GE1_TXCTL_MII_TXEN - - -
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49 GE1_TXCLKOUT MII_CRS - -
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50 GE1_RXCLK MSS_TWSI_SDA - -
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51 GE1_RXD[0] MSS_TWSI_SCK - -
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52 GE1_RXD[1] SYNCE1_CLK - SYNCE2_CLK
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53 GE1_RXD[2] - PTP_CLK -
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54 GE1_RXD[3] SYNCE2_CLK PTP_PCLK_OUT SYNCE1_CLK
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55 GE1_RXCTL_MII_RXDV - PTP_PULSE -
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56 - - - TDM_DRX
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57 - MSS_TWSI_SDA PTP_PCLK_OUT TDM_INTn
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58 - MSS_TWSI_SCK PTP_CLK TDM_RSTn
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59 MSS_GPIO[7] SYNCE2_CLK - TDM_FSYNC
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60 MSS_GPIO[6] - PTP_PULSE TDM_DTX
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61 MSS_GPIO[5] - PTP_CLK TDM_PCLK
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62 MSS_GPIO[4] SYNCE1_CLK PTP_PCLK_OUT -
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-------------------------------------------------------------------------------
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MPP# 0x5 0x6 0x7
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-------------------------------------------------------------------------------
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0 - PTP_PULSE MSS_TWSI_SDA
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1 - PTP_CLK MSS_TWSI_SCK
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2 MSS_UART_RXD PTP_PCLK_OUT TWSI1_SCK
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3 MSS_UART_TXD PCIe_RSTOUTn TWSI1_SDA
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4 MSS_UART_RXD UART1_CTS PCIe0_CLKREQ
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5 MSS_UART_TXD UART1_RTS PCIe1_CLKREQ
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6 AU_I2SEXTCLK SATA1_PRESENT_ACTIVEn PCIe2_CLKREQ
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7 SPI1_CSn[1] SATA0_PRESENT_ACTIVEn LED_DATA
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8 SPI1_CSn[0] UART0_CTS LED_STB
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9 SPI1_MOSI - PCIe_RSTOUTn
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10 SPI1_MISO UART0_CTS SATA1_PRESENT_ACTIVEn
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11 SPI1_CLK UART0_RTS LED_CLK
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12 - - -
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13 - - -
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14 AU_I2SEXTCLK SPI0_MISO SATA0_PRESENT_ACTIVEn
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15 - SPI0_MOSI -
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16 - - -
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17 - - -
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18 - - -
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19 - - -
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20 - - -
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21 - - -
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22 - - -
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23 AU_I2SMCLK - -
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24 AU_I2SLRCLK - -
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25 AU_I2SDO_SPDIFO - -
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26 AU_I2SBCLK - -
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27 SPI0_CSn[4] - -
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28 SPI0_CSn[5] PCIe2_CLKREQ PTP_PULSE
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29 SPI0_CSn[6] PCIe1_CLKREQ PTP_CLK
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30 SPI0_CSn[7] PCIe0_CLKREQ PTP_PCLK_OUT
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31 - PCIe_RSTOUTn -
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32 AU_I2SEXTCLK AU_I2SDI GE_MDIO
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33 AU_I2SMCLK SDIO_BUS_PWR -
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34 AU_I2SLRCLK SDIO_WR_PROTECT GE_MDC
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35 AU_I2SDO_SPDIFO SDIO_CARD_DETECT XG_MDIO
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36 AU_I2SBCLK SATA0_PRESENT_ACTIVEn XG_MDC
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37 MSS_TWSI_SCK SATA1_PRESENT_ACTIVEn GE_MDC
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38 MSS_TWSI_SDA SATA0_PRESENT_ACTIVEn GE_MDIO
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39 SPI0_CSn[1] - -
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40 PTP_PCLK_OUT SPI0_CLK UART1_TXD
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41 PTP_PULSE SPI0_MOSI UART1_RXD
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42 MSS_UART_TXD SPI0_MISO UART1_CTS
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43 MSS_UART_RXD SPI0_CSn[0] UART1_RTS
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44 - - UART0_RTS
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45 - - UART0_TXD
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46 - - UART1_RTS
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47 SPI1_CLK - UART1_TXD
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48 SPI1_MOSI - -
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49 SPI1_MISO - UART1_RXD
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50 SPI1_CSn[0] UART2_TXD UART0_RXD
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51 SPI1_CSn[1] UART2_RXD UART0_CTS
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52 SPI1_CSn[2] - UART1_CTS
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53 SPI1_CSn[3] - UART1_RXD
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54 - - -
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55 - - -
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56 AU_I2SDO_SPDIFO SPI0_CLK UART1_RXD
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57 AU_I2SBCLK SPI0_MOSI UART1_TXD
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58 AU_I2SDI SPI0_MISO UART1_CTS
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59 AU_I2SLRCLK SPI0_CSn[0] UART0_CTS
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60 AU_I2SMCLK SPI0_CSn[1] UART0_RTS
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61 AU_I2SEXTCLK SPI0_CSn[2] UART0_TXD
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62 SATA1_PRESENT_ACTIVEn SPI0_CSn[3] UART0_RXD
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-------------------------------------------------------------------------------
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MPP# 0x8 0x9 0xA
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-------------------------------------------------------------------------------
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0 UART0_RXD SATA0_PRESENT_ACTIVEn GE_MDIO
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1 UART0_TXD SATA1_PRESENT_ACTIVEn GE_MDC
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2 UART1_RXD SATA0_PRESENT_ACTIVEn XG_MDC
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3 UART1_TXD SATA1_PRESENT_ACTIVEn XG_MDIO
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4 UART3_RXD - GE_MDC
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5 UART3_TXD - GE_MDIO
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6 UART0_RXD PTP_PULSE -
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7 UART0_TXD PTP_CLK -
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8 UART2_RXD PTP_PCLK_OUT SYNCE1_CLK
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9 - - SYNCE2_CLK
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10 - - -
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11 UART2_TXD SATA0_PRESENT_ACTIVEn -
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12 - - -
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13 MSS_SPI_MISO - -
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14 MSS_SPI_CSn - -
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15 MSS_SPI_MOSI - -
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16 MSS_SPI_CLK - -
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17 - - -
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18 - - -
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19 - - -
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20 - - -
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21 - - -
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22 - - -
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23 - - -
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24 - - -
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25 - - -
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26 - - -
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27 GE_MDIO SATA0_PRESENT_ACTIVEn UART0_RTS
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28 GE_MDC SATA1_PRESENT_ACTIVEn UART0_CTS
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29 MSS_TWSI_SDA SATA0_PRESENT_ACTIVEn UART0_RXD
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30 MSS_TWSI_SCK SATA1_PRESENT_ACTIVEn UART0_TXD
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31 GE_MDC - -
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32 SDIO_V18_EN PCIe1_CLKREQ MSS_GPIO[0]
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33 XG_MDIO PCIe2_CLKREQ MSS_GPIO[1]
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34 - PCIe0_CLKREQ MSS_GPIO[2]
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35 GE_MDIO PCIe_RSTOUTn MSS_GPIO[3]
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36 GE_MDC PCIe2_CLKREQ MSS_GPIO[5]
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37 XG_MDC PCIe1_CLKREQ MSS_GPIO[6]
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38 XG_MDIO AU_I2SEXTCLK MSS_GPIO[7]
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39 SATA1_PRESENT_ACTIVEn MSS_GPIO[0]
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40 GE_MDIO SATA0_PRESENT_ACTIVEn MSS_GPIO[1]
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41 GE_MDC SATA1_PRESENT_ACTIVEn MSS_GPIO[2]
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42 XG_MDC SATA0_PRESENT_ACTIVEn MSS_GPIO[4]
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43 XG_MDIO SATA1_PRESENT_ACTIVEn MSS_GPIO[5]
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44 - - -
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45 - PCIe_RSTOUTn -
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46 - - -
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47 GE_MDC CLKOUT -
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48 XG_MDC - -
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49 GE_MDIO PCIe0_CLKREQ SDIO_V18_EN
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50 XG_MDIO - SDIO_PWR1[1]
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51 - - SDIO_PWR1[0]
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52 LED_CLK PCIe_RSTOUTn PCIe0_CLKREQ
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53 LED_STB - -
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54 LED_DATA - SDIO_HW_RST
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55 - - SDIO_LED
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56 - SATA1_PRESENT_ACTIVEn -
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57 - SATA0_PRESENT_ACTIVEn -
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58 LED_CLK - -
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59 LED_STB UART1_TXD -
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60 LED_DATA UART1_RXD -
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61 UART2_TXD SATA1_PRESENT_ACTIVEn GE_MDIO
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62 UART2_RXD SATA0_PRESENT_ACTIVEn GE_MDC
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-------------------------------------------------------------------------------
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MPP# 0xB 0xD 0xE
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-------------------------------------------------------------------------------
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0 - - -
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1 - - -
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2 - - -
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3 - - -
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4 - - -
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5 - - -
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6 - - -
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7 - - -
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8 - - -
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9 - - -
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10 - - -
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11 - CLKOUT_MPP_11 -
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12 - - -
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13 - - -
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14 - - -
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15 PTP_PULSE_CP2CP SAR_IN[5] -
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16 - SAR_IN[3] -
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17 - SAR_IN[6] -
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18 PTP_CLK_CP2CP SAR_IN[11] -
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19 WAKEUP_OUT_CP2CP SAR_IN[7] -
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20 - SAR_IN[9] -
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21 SEI_IN_CP2CP SAR_IN[8] -
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22 WAKEUP_IN_CP2CP SAR_IN[10] -
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23 LINK_RD_IN_CP2CP SAR_IN[4] -
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24 - - -
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25 - CLKOUT_MPP_25 -
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26 - SAR_IN[0] -
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27 REI_IN_CP2CP SAR_IN[1] -
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28 LED_DATA SAR_IN[2] -
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29 LED_STB AVS_FB_IN_CP2CP -
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30 LED_CLK SAR_IN[13] -
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31 - - -
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32 - SAR_CP2CP_OUT[0] -
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33 - SAR_CP2CP_OUT[1] -
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34 - SAR_CP2CP_OUT[2] -
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35 - SAR_CP2CP_OUT[3] -
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36 - CLKIN -
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37 LINK_RD_OUT_CP2CP SAR_CP2CP_OUT[4] -
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38 PTP_PULSE_CP2CP SAR_CP2CP_OUT[5] -
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39 - AVS_FB_OUT_CP2CP -
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40 - - -
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41 REI_OUT_CP2CP - -
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42 - SAR_CP2CP_OUT[9] -
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43 WAKEUP_OUT_CP2CP SAR_CP2CP_OUT[10] -
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44 PTP_CLK_CP2CP SAR_CP2CP_OUT[11] -
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45 - SAR_CP2CP_OUT[6] -
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46 - SAR_CP2CP_OUT[13] -
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47 - - -
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48 WAKEUP_IN_CP2CP SAR_CP2CP_OUT[7] -
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49 SEI_OUT_CP2CP SAR_CP2CP_OUT[8] -
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50 - - -
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51 - - -
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52 - - -
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53 SDIO_LED - -
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54 SDIO_WR_PROTECT - -
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55 SDIO_CARD_DETECT - -
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56 - - SDIO0_CLK
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57 - - SDIO0_CMD
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58 - - SDIO0_D[0]
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59 - - SDIO0_D[1]
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60 - - SDIO0_D[2]
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61 - - SDIO0_D[3]
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62 - - -
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